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74LVT162245 데이터시트 PDF




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부품번호 74LVT162245 기능
기능 Low Voltage 16-Bit Transceiver
제조업체 Fairchild Semiconductor
로고 Fairchild Semiconductor 로고


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74LVT162245 데이터시트, 핀배열, 회로
January 1999
Revised June 2005
74LVT162245 74LVTH162245
Low Voltage 16-Bit Transceiver with 3-STATE Outputs
and 25: Series Resistors in A Port Outputs
General Description
The LVT162245 and LVTH162245 contains sixteen non-
inverting bidirectional buffers with 3-STATE outputs and is
intended for bus oriented applications. The device is byte
controlled. Each byte has separate control inputs which
can be shorted together for full 16-bit operation. The T/R
inputs determine the direction of data flow through the
device. The OE inputs disable both the A and B ports by
placing them in a high impedance state.
The LVT162245 and LVTH162245 are designed with
equivalent 25: series resistance in both the HIGH and
LOW states on the A Port outputs. This design reduces line
noise in applications such as memory address drivers,
clock drivers, and bus transceivers/transmitters.
The LVTH162245 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
These non-inverting transceivers are designed for low volt-
age (3.3V) VCC applications, but with the capability to pro-
vide a TTL interface to a 5V environment. The LVT162245
and LVTH162245 are fabricated with an advanced
BiCMOS technology to achieve high speed operation simi-
lar to 5V ABT while maintaining a low power dissipation.
Features
s Input and output interface capability to systems at
5V VCC
s Bushold data inputs eliminate the need for external pull-
up resistors to hold unused inputs (74LVTH162245),
also available without bushold feature (74LVT162245).
s Live insertion/extraction permitted
s Power Up/Down high impedance provides glitch-free
bus loading
s A Port outputs include equivalent series resistance of
25: making external termination resistors unnecessary
and reducing overshoot and undershoot
s A Port outputs source/sink r12 mA.
B Port outputs source/sink 32 mA/64 mA
s Functionally compatible with the 74 series 162245
s Latch-up performance exceeds 500 mA
s ESD performance:
Human-body model ! 2000V
Machine model ! 200V
Charged-device model ! 1000V
s Also packaged in plastic Fine Pitch Ball Grid Array
(FBGA)
Ordering Code:
Order Number Package Number
Package Description
74LVT162245G
(Note 1)(Note 2)
BGA54A
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
(Preliminary)
74LVT162245MEA
(Note 2)
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
74LVT162245MTD
(Note 2)
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
74LVTH162245G
(Note 1)(Note 2)
BGA54A
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
74LVTH162245MEA
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
[TUBE]
74LVTH162245MEX
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
[TAPE and REEL]
74LVTH162245MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[TUBE]
74LVTH162245MTX
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[TAPE and REEL]
Note 1: Ordering code “G” indicates Trays.
Note 2: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 2005 Fairchild Semiconductor Corporation DS012446
www.fairchildsemi.com




74LVT162245 pdf, 반도체, 판매, 대치품
Absolute Maximum Ratings(Note 3)
Symbol
VCC
VI
VO
Parameter
Supply Voltage
DC Input Voltage
Output Voltage
IIK DC Input Diode Current
IOK DC Output Diode Current
IO DC Output Current
ICC
IGND
TSTG
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
Value
0.5 to 4.6
0.5 to 7.0
0.5 to 7.0
0.5 to 7.0
50
50
64
128
r64
r128
65 to 150
Recommended Operating Conditions
Conditions
Output in 3-STATE
Output in HIGH or LOW State (Note 4)
VI  GND
VO  GND
VO ! VCC Output at HIGH State
VO ! VCC Output at LOW State
Units
V
V
V
mA
mA
mA
mA
mA
qC
Symbol
Parameter
Min Max Units
VCC Supply Voltage
VI Input Voltage
IOH HIGH-Level Output Current
B Port
A Port
2.7
0
3.6
5.5
32
12
V
V
mA
IOL LOW-Level Output Current
B Port
A Port
64
mA
12
TA Free Air Operating Temperature
40 85
qC
't/'V
Input Edge Rate, VIN 0.8V2.0V, VCC 3.0V
0 10 ns/V
Note 3: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions
beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied.
Note 4: IO Absolute Maximum Rating must be observed.
DC Electrical Characteristics
Symbol
Parameter
VIK Input Clamp Diode Voltage
VIH Input HIGH Voltage
VIL Input LOW Voltage
VOH Output HIGH Voltage
A Port
B Port
VOL
Output LOW Voltage
A Port
B Port
II(HOLD)
(Note 5)
II(OD)
(Note 5)
II
IOFF
Bushold Input Minimum Drive
Bushold Input Over-Drive
Current to Change State
Input Current
Control Pins
Data Pins
Power Off Leakage Current
VCC
(V)
2.7
2.73.6
2.73.6
3.0
2.73.6
2.7
3.0
3.0
2.7
2.7
3.0
3.0
3.0
3.0
3.0
3.6
3.6
3.6
0
TA 40qC to 85qC
Min Max
1.2
2.0
0.8
2.0
VCC0.2
2.4
2.0
0.8
0.2
0.5
0.4
0.5
0.55
75
75
500
500
10
r1
5
1
r100
Units
Conditions
V II 18 mA
V VO d 0.1V or
V VO t VCC  0.1V
V IOH 12 mA
V IOH 100 PA
V IOH 8 mA
IOH 32 mA
V IOL 12 mA
V IOL 100 PA
IOL 24 mA
V IOL 16 mA
IOL 32 mA
IOL 64 mA
PA VI 0.8V
VI 2.0V
(Note 6)
PA
(Note 7)
VI 5.5V
PA VI 0V or VCC
VI 0V
VI VCC
PA 0V d VI or VO d 5.5V
www.fairchildsemi.com
4

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74LVT162245 전자부품, 판매, 대치품
Physical Dimensions inches (millimeters) unless otherwise noted
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
Package Number BGA54A
7 www.fairchildsemi.com

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