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74LVT162244 데이터시트 PDF




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부품번호 74LVT162244 기능
기능 Low Voltage 16-Bit Buffer/Line Driver
제조업체 Fairchild Semiconductor
로고 Fairchild Semiconductor 로고


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74LVT162244 데이터시트, 핀배열, 회로
March 1999
Revised June 2005
74LVT162244 74LVTH162244
Low Voltage 16-Bit Buffer/Line Driver
with 3-STATE Outputs
and 25: Series Resistors in the Outputs
General Description
The LVT162244 and LVTH162244 contain sixteen non-
inverting buffers with 3-STATE outputs designed to be
employed as a memory and address driver, clock driver, or
bus oriented transmitter/receiver. The device is nibble con-
trolled. Individual 3-STATE control inputs can be shorted
together for 8-bit or 16-bit operation.
The LVT162244 and LVTH162244 are designed with
equivalent 25: series resistance in both the HIGH and
LOW states of the output. This design reduces line noise in
applications such as memory address drivers, clock driv-
ers, and bus transceivers/transmitters.
The LVTH162244 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
These buffers and line drivers are designed for low-voltage
(3.3V) VCC applications, but with the capability to provide a
TTL interface to a 5V environment. The LVT162244 and
LVTH162244 are fabricated with an advanced BiCMOS
technology to achieve high speed operation similar to 5V
ABT while maintaining a low power dissipation.
Features
s Input and output interface capability to systems at
5V VCC
s Bushold data inputs eliminate the need for external pull-
up resistors to hold unused inputs (74LVTH162244),
also available without bushold feature (74LVT162244).
s Live insertion/extraction permitted
s Power Up/Power Down high impedance provides glitch-
free bus loading
s Outputs include equivalent series resistance of 25: to
make external termination resistors unnecessary and
reduce overshoot and undershoot
s Functionally compatible with the 74 series 162244
s Latch-up performance exceeds 500 mA
s ESD performance:
Human-body model ! 2000V
Machine model ! 200V
Charged-device ! 1000V
s Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA)
Ordering Code:
Order Number
Package
Number
Package Description
74LVT162244G
(Note 1)(Note 2)
BGA54A 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
74LVT162244MEA
(Note 2)
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
74LVT162244MTD
(Note 2)
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
74LVTH162244G
(Note 1)(Note 2)
BGA54A 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
74LVTH162244MEA
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
[Tube]
74LVTH162244MEX
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
[Tape and Reel]
74LVTH162244MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[Tube]
74LVTH162244MTX
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[Tape and Reel]
Note 1: Ordering code “G” indicates Trays.
Note 2: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 2005 Fairchild Semiconductor Corporation DS012445
www.fairchildsemi.com




74LVT162244 pdf, 반도체, 판매, 대치품
Absolute Maximum Ratings(Note 3)
Symbol
VCC
VI
VO
Parameter
Supply Voltage
DC Input Voltage
Output Voltage
IIK DC Input Diode Current
IOK DC Output Diode Current
IO DC Output Current
ICC
IGND
TSTG
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
Value
0.5 to 4.6
0.5 to 7.0
0.5 to 7.0
0.5 to 7.0
50
50
64
128
r64
r128
65 to 150
Recommended Operating Conditions
Conditions
Output in 3-STATE
Output in HIGH or LOW State (Note 4)
VI  GND
VO  GND
VO ! VCC Output at HIGH State
VO ! VCC Output at LOW State
Units
V
V
V
mA
mA
mA
mA
mA
qC
Symbol
Parameter
Min
Max
Units
VCC Supply Voltage
2.7 3.6
V
VI Input Voltage
0 5.5 V
IOH HIGH-Level Output Current
12 mA
IOL LOW-Level Output Current
12 mA
TA Free Air Operating Temperature
40 85
qC
't/'V
Input Edge Rate, VIN 0.8V2.0V, VCC 3.0V
0 10 ns/V
Note 3: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions
beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied.
Note 4: IO Absolute Maximum Rating must be observed.
DC Electrical Characteristics
Symbol
Parameter
VIK Input Clamp Diode Voltage
VIH Input HIGH Voltage
VIL Input LOW Voltage
VOH Output HIGH Voltage
VOL Output LOW Voltage
II(HOLD)
(Note 5)
II(OD)
(Note 5)
II
IOFF
IPU/PD
IOZL
IOZH
IOZH
ICCH
ICCL
ICCZ
Bushold Input Minimum Drive
Bushold Input Over-Drive
Current to Change State
Input Current
Control Pins
Data Pins
Power Off Leakage Current
Power Up/Down
3-STATE Current
3-STATE Output Leakage Current
3-STATE Output Leakage Current
3-STATE Output Leakage Current
Power Supply Current
Power Supply Current
Power Supply Current
VCC
(V)
2.7
2.73.6
2.73.6
2.73.6
3.0
2.7
3.0
3.0
3.0
3.6
3.6
3.6
0
01.5V
3.6
3.6
3.6
3.6
3.6
3.6
TA 40qC to 85qC
Min Max
1.2
2.0
0.8
VCC0.2
2.0
0.2
0.8
75
75
500
500
10
r1
5
1
r100
r100
5
5
10
0.19
5
0.19
Units
V
V
V
V
V
PA
PA
PA
PA
PA
PA
PA
PA
mA
mA
mA
Conditions
II 18 mA
VO d 0.1V or
VO t VCC  0.1V
IOH 100 PA
IOH 12 mA
IOL 100 PA
IOL 12 mA
VI 0.8V
VI 2.0V
(Note 6)
(Note 7)
VI 5.5V
VI 0V or VCC
VI 0V
VI VCC
0V d VI or VO d 5.5V
VO 0.5V to 3.0V
VI GND or VCC
VO 0.5V
VO 3.0V
VCC  VO d 5.5V
Outputs HIGH
Outputs LOW
Outputs Disabled
www.fairchildsemi.com
4

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74LVT162244 전자부품, 판매, 대치품
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
Package Number MS48A
7 www.fairchildsemi.com

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