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74LVT162240 데이터시트 PDF




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부품번호 74LVT162240 기능
기능 Low Voltage 16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs and 25ohm Series Resistors in the Outputs
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74LVT162240 데이터시트, 핀배열, 회로
June 1999
Revised June 1999
74LVT162240 • 74LVTH162240
Low Voltage 16-Bit Inverting Buffer/Line Driver
with 3-STATE Outputs and
25Series Resistors in the Outputs
General Description
The LVT162240 and LVTH162240 contain sixteen inverting
buffers with 3-STATE outputs designed to be employed as
a memory and address driver, clock driver, or bus oriented
transmitter/receiver. The device is nibble controlled. Indi-
vidual 3-STATE control inputs can be shorted together for
8-bit or 16-bit operation.
The LVT162240 and LVTH162240 are designed with
equivalent 25series resistance in both the HIGH and
LOW states of the output. This design reduces line noise in
applications such as memory address drivers, clock driv-
ers, and bus transceivers/transmitters.
The LVTH162240 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
These inverting buffers and line drivers are designed for
low-voltage (3.3V) VCC applications, but with the capability
to provide a TTL interface to a 5V environment. The
LVT162240 and LVTH162240 are fabricated with an
advanced BiCMOS technology to achieve high speed oper-
ation similar to 5V ABT while maintaining a low power dis-
sipation.
Features
s Input and output interface capability to systems at
5V VCC
s Outputs include equivalent series resistance of 25to
make external termination resistors unnecessary and
reduce overshoot and undershoot
s Bushold data inputs eliminate the need for external pull-
up resistors to hold unused inputs (74LVTH162240),
also available without bushold feature (74LVT162240).
s Live insertion/extraction permitted
s Power Up/Down high impedance provides glitch-free
bus loading
s Functionally compatible with the 74 series 162240
s Latch-up performance exceeds 500 mA
Ordering Code:
Order Number Package Number
Package Description
74LVT162240MEA
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74LVT162240MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
74LVTH162240MEA
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74LVTH162240MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
Description
OEn
I0–I15
O0–O15
Output Enable Inputs (Active LOW)
Inputs
3-STATE Outputs
© 1999 Fairchild Semiconductor Corporation DS012490
www.fairchildsemi.com




74LVT162240 pdf, 반도체, 판매, 대치품
DC Electrical Characteristics (Continued)
Symbol
Parameter
TA = −40°C to +85°C
VCC
(V)
Min Typ Max Units
(Note 3)
Conditions
ICCZ+
Power Supply Current
3.6
0.19
mA VCC VO 5.5V,
Outputs Disabled
ICC
Increase in Power Supply Current
(Note 7)
Note 3: All typical values are at VCC = 3.3V, TA = 25°C.
3.6
0.2 mA One Input at VCC 0.6V
Other Inputs at VCC or GND
Note 4: Applies to bushold versions only (74LVTH162240).
Note 5: An external driver must source at least the specified current to switch from LOW-to-HIGH.
Note 6: An external driver must sink at least the specified current to switch from HIGH-to-LOW.
Note 7: This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND.
Dynamic Switching Characteristics (Note 8)
Symbol
Parameter
VCC TA = 25°C
(V) Min Typ
VOLP
Quiet Output Maximum Dynamic VOL
3.3
0.8
VOLV
Quiet Output Minimum Dynamic VOL
3.3
0.8
Note 8: Characterized in SSOP package. Guaranteed parameter, but not tested.
Note 9: Max number of outputs defined as (n). n1 data inputs are driven 0V to 3V. Output under test held LOW.
Max
Units
V
V
Conditions
CL = 50 pF,
RL = 500
(Note 9)
(Note 9)
AC Electrical Characteristics
TA = −40°C to +85°C, CL = 50 pF, RL = 500
Symbol
Parameter
VCC = 3.3V ±0.3V
Min Typ Max
VCC = 2.7V
Min Max
Units
(Note 10)
tPLH Propagation Delay Data to Output
tPHL
1.0 4.0 1.0 4.8
ns
1.0 4.0 1.0 4.6
tPZH
tPZL
Output Enable Time
1.0 4.8 1.0 5.7
ns
1.0 4.9 1.0 6.1
tPHZ
tPLZ
Output Disable Time
2.0 4.9 2.0 5.4
ns
2.0 4.5 2.0 4.5
tOSHL
Output to Output Skew
1.0 1.0 ns
tOSLH
(Note 11)
Note 10: All typical values are at VCC = 3.3V, TA = 25°C.
Note 11: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
Capacitance (Note 12)
Symbol
Parameter
Conditions
CIN Input Capacitance
VCC = 0V, VI = 0V or VCC
COUT
Output Capacitance
VCC = 3.0V, VO = 0V or VCC
Note 12: Capacitance is measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012.
Typical
4
8
Units
pF
pF
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부품번호상세설명 및 기능제조사
74LVT162240

Low Voltage 16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs and 25 Series Resistors in the Outputs

Fairchild Semiconductor
Fairchild Semiconductor
74LVT162240

Low Voltage 16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs and 25ohm Series Resistors in the Outputs

Fairchild Semiconductor
Fairchild Semiconductor

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