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74LVT16244 데이터시트 PDF




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부품번호 74LVT16244 기능
기능 Low Voltage16-Bit Buffer/Line Driver with 3-STATE Outputs
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74LVT16244 데이터시트, 핀배열, 회로
March 1999
Revised June 2005
74LVT16244 74LVTH16244
Low Voltage16-Bit Buffer/Line Driver
with 3-STATE Outputs
General Description
The LVT16244 and LVTH16244 contain sixteen non-invert-
ing buffers with 3-STATE outputs designed to be employed
as a memory and address driver, clock driver, or bus ori-
ented transmitter/receiver. The device is nibble controlled.
Individual 3-STATE control inputs can be shorted together
for 8-bit or 16-bit operation.
The LVTH16244 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
These buffers and line drivers are designed for low-voltage
(3.3V) VCC applications, but with the capability to provide a
TTL interface to a 5V environment. The LVT16244 and
LVTH16244 are fabricated with an advanced BiCMOS
technology to achieve high speed operation similar to 5V
ABT while maintaining a low power dissipation
Features
s Input and output interface capability to systems at
5V VCC
s Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs (74LVTH16244),
also available without bushold feature (74LVT16244).
s Live insertion/extraction permitted
s Power Up/Down high impedance provides glitch-free
bus loading
s Outputs source/sink 32 mA/64 mA
s Functionally compatible with the 74 series 16244
s Latch-up performance exceeds 500 mA
s ESD performance:
Human-body model !2000V
Machine model !200V
Charged-drive model !1000V
s Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA)
Ordering Code:
Order Number
Package
Number
Package Description
74LVT16244G
(Note 1)(Note 2)
BGA54A
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
(Preliminary)
74LVT16244MEA
(Note 2)
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
74LVT16244MTD
(Note 2)
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
74LVTH16244G
(Note 1)(Note 2)
BGA54A
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
74LVTH16244MEA
(Note 2)
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
74LVTH16244MTD
(Note 2)
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Note 1: Ordering code “G” indicates Trays.
Note 2: Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
© 2005 Fairchild Semiconductor Corporation DS500151
www.fairchildsemi.com




74LVT16244 pdf, 반도체, 판매, 대치품
DC Electrical Characteristics (Continued)
Symbol
Parameter
ICCH
ICCL
ICCZ
ICCZ
Power Supply Current
Power Supply Current
Power Supply Current
Power Supply Current
VCC
TA 40qC to 85qC
Units
(V) Min Max
3.6
0.19
mA
3.6 5.0 mA
3.6
0.19
mA
3.6
0.19
mA
'ICC
Increase in Power Supply Current
(Note 8)
3.6
0.2 mA
Note 5: Applies to bushold versions only (LVTH16244).
Note 6: An external driver must source at least the specified current to switch from LOW-to-HIGH.
Note 7: An external driver must sink at least the specified current to switch from HIGH-to-LOW.
Note 8: This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND.
Conditions
Outputs High
Outputs Low
Outputs Disabled
VCC d VO d 5.5V,
Outputs Disabled
One Input at VCC  0.6V
Other Inputs at VCC or GND
Dynamic Switching Characteristics (Note 9)
Symbol
Parameter
VCC TA 25qC
(V) Min Typ Max
VOLP
VOLV
Quiet Output Maximum Dynamic VOL
Quiet Output Minimum Dynamic VOL
3.3
3.3
0.8
0.8
Note 9: Characterized in SSOP package. Guaranteed parameter, but not tested.
Note 10: Max number of outputs defined as (n). n1 data inputs are driven 0V to 3V. Output under test held LOW.
Units
V
V
Conditions
CL 50 pF, RL 500:
(Note 10)
(Note 10)
AC Electrical Characteristics
Symbol
Parameter
TA 40qC to 85qC
CL 50 pF, RL 500:
VCC 3.3V r 0.3V
VCC 2.7V
Units
Min Max Min Max
tPLH Propagation Delay Data to Output
tPHL
1.2 3.5 1.2 3.9
ns
1.2 3.5 1.2 3.9
tPZH
tPZL
Output Enable Time
1.2 4.0 1.2 5.0
ns
1.2 5.0 1.2 6.5
tPHZ
tPLZ
Output Disable Time
2.0 4.7 2.0 5.2
ns
1.5 4.2 1.5 4.4
tOSHL
tOSLH
Output to Output Skew
(Note 11)
1.0 1.0 ns
Note 11: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
Capacitance (Note 12)
Symbol
Parameter
Conditions
CIN Input Capacitance
COUT
Output Capacitance
Note 12: Capacitance is measured at frequency f
VCC 0V, VI 0V or VCC
VCC 3.0V, VO 0V or VCC
1 MHz, per MIL-STD-883, Method 3012.
Typical
4
8
Units
pF
pF
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74LVT16244 전자부품, 판매, 대치품
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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