|
|
|
부품번호 | 74LVT16240 기능 |
|
|
기능 | Low Voltage 16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs | ||
제조업체 | Fairchild Semiconductor | ||
로고 | |||
전체 6 페이지수
March 1999
Revised March 1999
74LVT16240 • 74LVTH16240
Low Voltage 16-Bit Inverting Buffer/Line Driver
with 3-STATE Outputs
General Description
The LVT16240 and LVTH16240 contain sixteen inverting
buffers with 3-STATE outputs designed to be employed as
a memory and address driver, clock driver, or bus-oriented
transmitter/receiver. The device is nibble controlled.
Individual 3-STATE control inputs can be shorted together
for 8-bit or 16-bit operation.
The LVTH16240 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
These buffers and line drivers are designed for low-voltage
(3.3V) VCC applications, but with the capability to provide a
TTL interface to a 5V environment. The LVT16240 and
LVTH16240 are fabricated with an advanced BiCMOS
technology to achieve high speed operation similar to 5V
ABT while maintaining a low power dissipation.
Features
s Input and output interface capability to systems at
5V VCC
s Bushold data inputs eliminate the need for external pull-
up resistors to hold unused inputs (74LVTH16240), also
available without bushold feature (74LVT16240).
s Live insertion/extraction permitted
s Power Up/Down high impedance provides glitch-free
bus loading
s Outputs source/sink −32 mA/+64 mA
s Functionally compatible with the 74 series 16240
s Latch-up performance exceeds 500 mA
Ordering Code:
Order Number
Package
Number
Package Description
74LVT16240MEA
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74LVT16240MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
74LVTH16240MEA
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74LVTH16240MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
© 1999 Fairchild Semiconductor Corporation DS012025.prf
www.fairchildsemi.com
DC Electrical Characteristics (Continued)
Symbol
Parameter
IOZH+
ICCH
ICCL
ICCZ
ICCZH+
3-STATE Output Leakage Current
Power Supply Current
Power Supply Current
Power Supply Current
Power Supply Current
TA =−40°C to +85°C
VCC
(V)
Min Typ
Max
Units
(Note 10)
3.6 10 µA
3.6
0.19
mA
3.6 5 mA
3.6
0.19
mA
3.6
0.19
mA
∆ICC
Increase in Power Supply Current
(Note 7)
3.6
0.2 mA
Note 3: All typical values are at VCC = 3.3V, TA = 25°C.
Note 4: Applies to bushold versions only (LVTH16240).
Note 5: An external driver must source at least the specified current to switch from LOW to HIGH.
Note 6: An external driver must sink at least the specified current to switch from HIGH to LOW.
Note 7: This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND.
Conditions
VCC < VO ≤ 5.5V
VI = GND or VCC,
Outputs High
VI = GND or VCC,
Outputs Low
VI = GND or VCC,
Outputs Disabled
VI = GND or VCC,
VCC ≤ VO ≤ 5.5V,
Outputs Disabled
One Input at VCC − 0.6V
Other Inputs at VCC or GND
Dynamic Switching Characteristics (Note 8)
Symbol
Parameter
VCC TA = 25°C
(V) Min Typ
VOLP
Quiet Output Maximum Dynamic VOL
3.3
VOLV
Quiet Output Minimum Dynamic VOL
3.3
Note 8: Characterized in SSOP package. Guaranteed parameter, but not tested.
0.8
−0.8
Note 9: Max number of outputs defined as (n). n−1 data inputs are driven 0V to 3V. Output at LOW.
Max
Units
V
V
Conditions
CL = 50 pF, RL = 500Ω
(Note 9)
(Note 9)
AC Electrical Characteristics
TA = −40°C to +85°C, CL = 50 pF, RL = 500Ω
Symbol
Parameter
VCC = 3.3V ±0.3V
Min Typ Max
VCC = 2.7V
Min Max
Units
(Note 10)
tPLH Propagation Delay Data to Output
tPHL
1.0
1.0
3.5 1.0 4.2
ns
3.5 1.0 4.0
tPZH
tPZL
Output Enable Time
1.0 4.0 1.0 4.9
ns
1.2 4.8 1.2 6.1
tPHZ
tPLZ
Output Disable Time
1.7 4.7 1.7 5.2
ns
1.7 4.2 1.7 4.4
tOSHL
Output to Output Skew
1.0 1.0 ns
tOSLH
(Note 11)
Note 10: All typical values are at VCC = 3.3V, TA = 25°C.
Note 11: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH to LOW (tOSHL) or LOW to HIGH (tOSLH).
Capacitance (Note 12)
Symbol
Parameter
Conditions
CIN Input Capacitance
VCC = 0V, VI = 0V or VCC
COUT
Output Capacitance
VCC = 3.0V, VO = 0V or VCC
Note 12: Capacitance is measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012.
Typical
4
8
Units
pF
pF
www.fairchildsemi.com
4
4페이지 | |||
구 성 | 총 6 페이지수 | ||
다운로드 | [ 74LVT16240.PDF 데이터시트 ] |
당사 플랫폼은 키워드, 제품 이름 또는 부품 번호를 사용하여 검색할 수 있는 |
구매 문의 | 일반 IC 문의 : 샘플 및 소량 구매 ----------------------------------------------------------------------- IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한 광범위한 전력 반도체를 판매합니다. 전력 반도체 전문업체 상호 : 아이지 인터내셔날 사이트 방문 : [ 홈페이지 ] [ 블로그 1 ] [ 블로그 2 ] |
부품번호 | 상세설명 및 기능 | 제조사 |
74LVT16240 | Low Voltage 16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs | Fairchild Semiconductor |
74LVT16240 | Low Voltage 16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs | Fairchild Semiconductor |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |