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PDF KS57P21408 Data sheet ( Hoja de datos )
| Número de pieza | KS57P21408 | |
| Descripción | (KS57C21408 - KS57P21408) single-chip CMOS microcontroller | |
| Fabricantes | Samsung semiconductor | |
| Logotipo |  |
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KS57C21408/C21418/P21408
1 PRODUCT OVERVIEW
PRODUCT OVERVIEW
OVERVIEW
The KS57C21408/C21418/P21408 is a SAM47 core-based 4-bit CMOS single-chip microcontroller. It has a
timer/counter and LCD drivers.
The KS57P21408 is especially suited for use in data bank, telephone and LCD general purpose.
It is built around the SAM47 core CPU and contains ROM, RAM, 39 I/O lines, programmable timer/counter,
buzzer output, enough LCD dot matrix, and segment drive pins.
The KS57C21408/C21418/P21408 can be used for dedicated control functions in a variety of applications, and is
especially designed for multi data bank, telephone and LCD game.
OTP
The KS57C21408/C21418 microcontroller is also available in OTP (One Time Programmable) version,
KS57P21408. KS57P21408 microcontroller has an on-chip 8 K-byte one-time-programable EPROM instead of
masked ROM. The KS57P21408 is comparable to KS57C21408/C21418, both in function and in pin
configuration.
1-1
1 page  
KS57C21408/C21418/P21408
PRODUCT OVERVIEW
PIN DESCRIPTIONS
Table 1-1. Pin Descriptions
Pin Name
P0.0 - P0.3
P1.0
P1.1
P2.0
P2.1
P4.0
P4.1
P4.2
P5.0 - P5.3
P6.0 - P6.3
P7.0 - P7.3
P8.0 - P8.15
SEG16-SEG59
Pin
Type
Description
I 4-bit input port.
1 and 4-bit read, and test are possible.
Pull-up registers.
I 2-bit Input port.
1 and 4-bit read, and test are possible, 2-bit pull-up
resistors are assignable by software.
I/O 2-bit I/O port. 1 and 4-bit read/write, and test are
possible.
Each individual pin can be specified as input or
output.
2-bit pull-up resistors are assignable by software.
Pull-up resistors are automatically disabled for
output pins.
I/O 4-bit I/O port. 1, 4, and 8-bit read/write, and test are
possible.
4-pin unit can be specified as input or output.
4-bit pull-up resistors are assignable by software.
Pull-up resistors are automatically disabled for
output pins.
Individual pins are software configurable as open-
drain or push-pull output.
I/O 4-bit I/O port. 1, 4,and 8-bit read/write, and test are
possible.
Each individual pin can be specified as input or
output.
4-bit pull-up resistors are assignable by software.
Pull-up resistors are automatically disabled for
output pins.
4-bit I/O port. 1, 4, and 8-bit read/write, and test are
possible.
4-pin unit can be specified as input or output.
4-bit pull-up resistors are assignable by software.
Pull-up resistors are automatically disabled for
output pins.
O 4-bit controllable output.
(Dual function as segment output pins)
LCD segment display signal output.
SEG0 - SEG15
COM0 - COM8
LCD segment display signal output.
LCD common signal output.
INT0 - INT1
KS0 - KS7
K0 - K3
I External interrupts. The triggering edge for INT0,
and INT1 is selectable
I/O Quasi-interrupt input for falling edge detection.
I Vector interrupt input
K0 - K3: falling edge detection
Circuit Pin
Type Number
A-1 35-32
A-3 37
36
D 23
24
E 29
E-1 30
E-1 31
E-1 25-28
D-1 7-10
11-14
H-9 42-57
H-10
H-9
H-11
58-100
,1
42-57
38-41
2-6
37-36
7-14
35-32
Share Pin
K0-K3
INT0
INT1
BUZ
CLO
TCL0
TCLO0
KS0 - KS3
KS4 - KS7
SEG0 -
SEG15
-
P8.0 - P8.15
-
P1.0 -P1.1
P6.0 - P7.3
P0.0 - P0.3
1-5
5 Page 
KS57C21408/C21418/P21408
13 ELECTRICAL DATA
ELECTRICAL DATA
OVERVIEW
In this section, information on KS57C21408/C21418/P21408 electrical characteristics is presented as tables and
graphics. The information is arranged in the following order:
STANDARD ELECTRICAL CHARACTERISTICS
— Absolute maximum ratings
— D.C electrical characteristics
— Main-system clock oscillator characteristics
— Sub-system clock oscillator characteristics
— I/O capacitance
— A.C electrical characteristics
— Operating voltage range
MISCELLANEOUS TIMING WAVEFORMS
— A.C timing measurement point
— Clock timing measurement at Xin
— Clock timing measurement at XTin
— TCL0 timing
— Input timing for RESET
— Input timing for external interrupts
STOP MODE CHARACTERISTICS AND TIMING WAVEFORMS
— RAM data retention supply voltage in stop mode
— Stop mode release timing when initiated by RESET
— Stop mode release timing when initiated by an interrupt request
13–1
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet KS57P21408.PDF ] | |
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