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PDF CY7C09449PV-AC Data sheet ( Hoja de datos )
| Número de pieza | CY7C09449PV-AC | |
| Descripción | 128 Kb Dual-Port SRAM with PCI Bus Controller (PCI-DP) | |
| Fabricantes | Cypress Semiconductor | |
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09449PV
CY7C09449PV-AC
128 Kb Dual-Port SRAM with PCI Bus
Controller (PCI-DP)
Features
• 128 Kb of dual-ported shared memory
• Master and Target PCI Specification 2.2 compliant in-
terface
• Embedded host bridge capability
• Direct interface to many microprocessors
• I2O message transport unit; includes four 32-bit, 32-
entry FIFO
• Local bus clock rates up to 50 MHz
• Single 3.3V Power Supply including compatibility with
3V and 5V PCI Bus signaling
• 160-pin thin plastic quad flat package
Introduction
The CY7C09449PV is one of the PCI interface controllers in
the Cypress Semiconductor PCI-DP™ family. The
CY7C09449PV provides a PCI master/target interface with di-
rect connections to many popular microprocessors. It provides
128 Kb of dual-port SRAM that is used as shared memory
between the local microprocessor and the PCI bus. An I2O
message unit, complete with message queues and interrupt
capability, is also provided. The CY7C09449PV allows the de-
signer to interface an application to the PCI bus in a straight-
forward, inexpensive way.
Functional Overview
A primary resource within the CY7C09449PV is its 128 Kb of
dual-port memory. This memory is interfaced to both the PCI
bus and to a local microprocessor bus. This shared memory
can be accessed as a target from both buses at the same time
for inter-process communication. From either the local or PCI
bus the CY7C09449PV can be directed to become a PCI bus
master to move data into or out of the internal shared memory
as a direct memory access (DMA). The CY7C09449PV can
DMA across the PCI bus any number of 32-bit double words
(DWORD), up to 16K bytes. It uses the full bursting capabilities
of the PCI bus for maximum efficiency and can transfer data
over the full 32-bit PCI address space.
The CY7C09449PV implements optional requirements of the
PCI specification by selecting the optimum PCI command for
each transaction it masters to the PCI bus. This maximizes
overall efficiency of the system platform. PCI bridging func-
tions (PCI-to-PCI and Host-to-PCI bridges) use the commands
to enhance prefetch and cache coherency operations. The
CY7C09449PV requests and gains access to the PCI bus as
any master. It does not, within itself, include a PCI bus arbitra-
tion function. Standard PC PCI buses include this function;
embedded systems may need to implement this function.
The CY7C09449PV provides a direct access mechanism from
the local bus to the PCI bus. With it, the local processor can
direct the CY7C09449PV to run a PCI bus master cycle of any
kind to any address. This means that the CY7C09449PV can
run PCI configuration cycles allowing it to be used as a host
bridge.
The CY7C09449PV is composed of a number of shared re-
sources that allow effective data movement between the local
bus and the PCI bus.
Features
Introduction
Functional Overview
Pin Configuration
Pin Description
PCI Bus
Local Bus
Timing Diagrams
I2C Serial Port and Auto-Configuration
Operations Registers
Performance Characteristics
CY7C09449PV Operations
Ordering Information
Package Diagram
Table of Contents
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Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-06061 Rev. *A
Revised December 27, 2002
1 page  
CY7C09449PV-AC
Pin Description
The Pin Type for CY7C09449PV is defined as follows:
in Input is a standard input-only signal.
out Standard output driver.
t/s Three-state is an output or bidirectional signal.
s/t/s Sustained Three-State is an active LOW, three-state capable signal driven by only one bus agent at a time.
When ownership is passed to another agent, the signal is driven HIGH for one clock, and then three-stated for
an additional clock before being driven by the new owner.
o/d Open Drain signals allow multiple devices to share the pin as a wired-OR.
o/c Open Collector signals allow multiple devices to share the pin as a wired-OR.
PCI Bus Signals
Signal Name Type
CLK in
RST in
AD[31:0]
t/s
C/BE[3:0]
PAR
FRAME
IRDY
TRDY
STOP
IDSEL
DEVSEL
t/s
t/s
s/t/s
s/t/s
s/t/s
s/t/s
in
s/t/s
Description
Clock: This is the PCI Bus clock and is the timing reference for all PCI bus transactions. The
CY7C09449PV can operate with a 33-MHz PCI bus interface.
RESET: This signal is the PCI bus reset. It is one of the few PCI signals which may be asserted or
deasserted asynchronously to the PCI bus clock (CLK).
Address and Data: These signals represent the PCI bus address and data signals multiplexed on
the same PCI pins. Information on these pins is identified as an address during the clock cycle in
which the signal FRAME is first asserted. This is termed the “address phase” of a bus transaction.
Information on these pins represents valid read or write data when both IRDY and TRDY are asserted,
based on the current cycle type as defined on the C/BE lines during the address phase. This condition
is termed the “data phase” of a bus transaction.
Command and Byte Enables: These pins are used with the AD[31:0] pins. During the address phase
of a bus operation, they identify the bus command to be performed. During the data phase of a bus
operation they identify which bytes are involved.
Parity: This PCI bus pin represents the even parity across the A/D[31:00] and C/BE[3:0] pins (36
pins) and is generated with a one clock delay.
Cycle Frame: This PCI bus pin is asserted by the current bus master to signify the beginning of a
bus transaction. Data transfers may continue in burst mode while FRAME remains asserted. When
FRAME is deasserted it indicates that the transaction is in the final data phase.
Initiator Ready: This signal is driven by the current bus master (initiator) and asserted to indicate its
ability to complete the current data phase. Data is transferred when both IRDY and TRDY are asserted,
otherwise wait cycles will occur.
Target Ready: This signal is driven by the selected bus target and asserted when that target is ready
to complete the current data phase. Data is transferred when both IRDY and TRDY are asserted,
otherwise wait cycles will occur.
Stop: The STOP signal is driven by the selected bus target and is asserted when it wishes to cease
the current data transaction.
Initialization Device Select: This signal is used to gain access to the PCI configuration register space
of a given PCI Bus agent.
Device Select: The DEVSEL signal is driven and asserted by the currently selected PCI bus target
based on the current address and that target’s assigned address range. Bus masters examine this
signal to determine whether the desired device is present.
Document #: 38-06061 Rev. *A
Page 5 of 50
5 Page 
CY7C09449PV-AC
This register provides the base address of the CY7C09449PV
memory map. Bits [31–15] are read/write, indicating to the sys-
tem BIOS that the shared memory space is 32 K bytes. If a
PCI memory transaction has address bits [31–15] matching
the contents of this register and memory accesses are en-
abled (by Command register bit 1), then the CY7C09449PV
chip will acknowledge and accept the transfer.
Base Address Register 1 (I/O Type Access)
Address: 0x17 - 0x14
Default Value: 0x00000001
Read all 32 bits, Write bits [31–3]
This register provides the base address of the CY7C09449PV
I/O pointer space. Bits [31–3] are read/write, indicating to the
system BIOS that the I/O pointer space is 8 bytes. If a PCI I/O
transaction has address bits [31–3] matching the contents of
this and I/O accesses are enabled (by Command register bit
0), then the CY7C09449PV will acknowledge and accept the
transfer.
Cardbus CIS Pointer
Address - 0x2B - 0x28
Default Value: 0x00000000
Read-only: Can be initialized from the external memory ac-
cessed via the I2C-compatible serial interface.
This register contains the Cardbus Card Information Structure
(CIS). Using the I2C-compatible serial interface for initializa-
tion provides a method to allow a manufacturer to load their
own CIS pointer value.
Subsystem Vendor ID
Address: 0x2D - 0x2C
Default Value: 0x0000
Read-only: Can be initialized from the external memory ac-
cessed via the I2C-compatible serial interface.
This 2-byte register contains the subsystem vendor ID chosen
by the manufacturer. Using the I2C-compatible serial interface
for initialization provides a method to allow a manufacturer to
load their own subsystem vendor ID.
Subsystem Device ID
Address: 0x2F - 0x2E
Default Value: 0x0000
Read-only: Can be initialized from the external memory ac-
cessed via the I2C-compatible serial interface.
This 2-byte register contains the subsystem device ID chosen
by the manufacturer. Using the I2C-compatible serial interface
for initialization provides a method to allow a manufacturer to
load their own subsystem device ID.
Interrupt Line
Address: 0x3C
Default Value: 0x00
Read/Write
This single-byte register contains the interrupt line routing.
Interrupt Pin
Address: 0x3D
Default Value: 0x00
Read-only: Can be initialized from the external memory ac-
cessed via the I2C-compatible serial interface.
This single-byte register contains the interrupt pin information.
The default value indicates that the CY7C09449PV chip is not
connected to the interrupts on the PCI bus. Using the I2C-
compatible serial interface for initialization provides a method
to allow a manufacturer to specify which interrupt pin is on the
bus. Only bits [2–0] are implemented. All four Interrupt num-
bers are supported, (INTA through INTD).
MIN_GNT
Address: 0x3E
Default Value: 0x00
Read-only: Can be initialized from the external memory ac-
cessed via the I2C-compatible serial interface.
This single-byte register contains the minimum grant time in 1/
4 microsecond increments needed for efficient operation. The
default value indicates the add-in card has no major require-
ments for the setting of the latency timer. The latency timer
governs how long a burst transaction may use the PCI bus.
Whatever the value, the CY7C09449PV itself does not use the
MIN_GNT data. It is used as a means to communicate system
requirements to the host. Using the I2C-compatible serial in-
terface for initialization provides a method to allow a manufac-
turer to load their own minimum grant time reflective of their
add-in card requirements.
MAX_LAT
Address: 0x3F
Default Value: 0x00
Read-only: Can be initialized from the external memory ac-
cessed via the I2C-compatible serial interface.
This single-byte register contains the minimum latency time in
1/4 microsecond increments needed for efficient operation.
The default value indicates the add-in card has no major re-
quirements for how soon it needs access to the PCI bus once
it has requested an access. Whatever the value, the
CY7C09449PV itself does not use MAX_LAT data. It is used
as a means to communicate system requirements to the host.
Using the I2C-compatible serial interface for initialization pro-
vides a method to allow a manufacturer to load their own min-
imum latency time reflective of their add-in card requirements.
PCI Bus Commands
All Memory and I/O commands are supported as target and
master.
• I/O Read
C/BE[3:0] = 0x2
• I/O Write
C/BE[3:0] = 0x3
• Memory Read
C/BE[3:0] = 0x6
• Memory Write
C/BE[3:0] = 0x7
• Memory Read Multiple
C/BE[3:0] = 0xC
• Memory Read Line
C/BE[3:0] = 0xE
• Memory Write and Invalidate C/BE[3:0] = 0xF
All Configuration commands are supported as target and mas-
ter. Additionally, the CY7C09449PV can perform these ac-
Document #: 38-06061 Rev. *A
Page 11 of 50
11 Page | ||
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| PDF Descargar | [ Datasheet CY7C09449PV-AC.PDF ] | |
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