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PDF CY7C09379 Data sheet ( Hoja de datos )
| Número de pieza | CY7C09379 | |
| Descripción | (CY7C09279 - CY7C09289) 32K/64K X 16/18 Synchronous Dual Port Static RAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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25/0251
CY7C09279/89
CY7C09379/89
32K/64K x16/18
Synchronous Dual Port Static RAM
Features
• True dual-ported memory cells which allow simulta-
neous access of the same memory location
• Six Flow-Through/Pipelined devices
— 32K x 16/18 organization (CY7C09279/379)
— 64K x 16/18 organization (CY7C09289/389)
• Three Modes
— Flow-Through
— Pipelined
— Burst
• Pipelined output mode on both ports allows fast 100-
MHz cycle time
• 0.35-micron CMOS for optimum speed/power
• High-speed clock to data access 6.5[1]/7.5/9/12 ns
(max.)
• Low operating power
— Active = 195 mA (typical)
— Standby = 0.05 mA (typical)
• Fully synchronous interface for easier operation
• Burst counters increment addresses internally
— Shorten cycle times
— Minimize bus noise
— Supported in Flow-Through and Pipelined modes
• Dual Chip Enables for easy depth expansion
• Upper and Lower Byte Controls for Bus Matching
• Automatic power-down
• Commercial and Industrial temperature ranges
• Available in 100-pin TQFP
• Pin-compatible and functionally equivalent to IDT70927
and IDT709279
Logic Block Diagram
R/WL
UBL
R/WR
UBR
CE0L
CE1L
LBL
OEL
1
0
0/1
1 CE0R
0 CE1R
0/1 LBR
OER
FT/PipeL
[2]
I/O8/9L–I/O15/17L
1b 0b 1a 0a
0/1 b
a
8/9
[3]
I/O0L–I/O7/8L
[4]
A0L–A14/15L
CLKL
ADSL
CNTENL
CNTRSTL
8/9
15/16
Counter/
Address
Register
Decode
I/O
Control
I/O
Control
True Dual-Ported
RAM Array
0a 1a 0b 1b
a b 0/1
8/9
FT/PipeR
[2]
I/O8/9R–I/O15/17R
Counter/
Address
Register
Decode
8/9
15/16
[3]
I/O0R–I/O7/8R
[4]
A0R–A14/15R
CLKR
ADSR
CNTENR
CNTRSTR
Notes:
1. See page 6 for Load Conditions.
2. I/O8–I/O15 for x16 devices; I/O9–I/O17 for x18 devices.
3. I/O0–I/O7 for x16 devices. I/O0–I/O8 for x18 devices.
4. A0–A14 for 32K; A0–A15 for 64K devices.
For the most recent information, visit the Cypress web site at www.cypress.com
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-06040 Rev. **
Revised September 19, 2001
1 page  
CY7C09279/89
CY7C09379/89
Electrical Characteristics Over the Operating Range
CY7C09279/89
CY7C09379/89
-6[1] -7
-9
-12
Parameter
Description
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
VOH Output HIGH Voltage
2.4
2.4
2.4
2.4
(VCC = Min., IOH = –4.0 mA)
V
VOL Output LOW Voltage
(VCC = Min., IOH = +4.0 mA)
0.4 0.4 0.4 0.4 V
VIH Input HIGH Voltage
2.2
2.2
2.2
2.2
V
VIL Input LOW Voltage
0.8 0.8 0.8 0.8 V
IOZ
Output Leakage Current
–10
10 –10
10 –10
10 –10
10 µA
ICC
Operating Current
Com’l.
250 450
235 420
215 360
195 300 mA
(VCC = Max.,
IOUT = 0 mA)
Ind.[9]
245 410
mA
Outputs Disabled
ISB1
Standby Current (Both Com’l.
Ports TTL Level)[10]
CEL & CER ≥ VIH,
Ind.[9]
45 115
f = fMAX
40 105
35 95
50 110
30 85 mA
mA
ISB2
Standby Current (One Com’l.
Port TTL Level)[10]
CEL | CER ≥ VIH,
Ind.[9]
175 235
160 220
145 205
160 220
125 190 mA
mA
f = fMAX
ISB3
Standby Current (Both Com’l.
Ports CMOS Level)[10]
CEL & CER ≥ VCC –
Ind.[9]
0.05 0.5
0.05 0.5
0.05 0.5
0.05 0.5
0.05 0.5 mA
mA
0.2V, f = 0
ISB4
Standby Current (One Com’l.
Port CMOS Level)[10]
CEL | CER ≥ VIH,
Ind.[9]
160 200
f = fMAX
145 185
130 170
145 185
110 150 mA
mA
Capacitance
Parameter
Description
Test Conditions
Max.
Unit
CIN
COUT
Input Capacitance
Output Capacitance
TA = 25°C, f = 1 MHz,
VCC = 5.0V
10 pF
10 pF
Note:
10. CEL and CER are internal signals. To select either the left or right port, both CE0 AND CE1 must be asserted to their active states (CE0 ≤ VIL and CE1 ≥ VIH).
Document #: 38-06040 Rev. **
Page 5 of 18
5 Page 
CY7C09279/89
CY7C09379/89
Switching Waveforms (continued)
Flow-Through Read-to-Write-to-Read (OE = VIL)[15, 17, 24, 25]
tCYC1
tCH1
tCL1
CLK
CE0
tSC
tHC
CE1
R/W
tSW
ADDRESS
DATAIN
tSA
tHW
An
tHA
tCD1
An+1
tCD1
tSW tHW
An+2
An+2
tSD
Dn+2
An+3
tHD
tCD1
DATAOUT
Qn
tDC
READ
Qn+1
tCKHZ
NO
OPERATION
Flow-Through Read-to-Write-to-Read (OE Controlled)[15, 17, 24, 25]
tCYC1
tCH1
tCL1
WRITE
tCKLZ
CLK
An+4
tCD1
Qn+3
tDC
READ
CE0
tSC
CE1
R/W
tSW
ADDRESS
DATAIN
tSA
DATAOUT
OE
tHC
tSW tHW
tHW
An An+1
An+2
An+3
tHA
tCD1
tSD tHD
tDC Dn+2
Dn+3
Qn
tOHZ
READ
WRITE
An+4
An+5
tOE
tCD1
tCKLZ
tCD1
Qn+4
tDC
READ
Document #: 38-06040 Rev. **
Page 11 of 18
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet CY7C09379.PDF ] | |
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