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T89C51CC01 데이터시트 PDF




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부품번호 T89C51CC01 기능
기능 Enhanced 8-Bit Microcontroller
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T89C51CC01 데이터시트, 핀배열, 회로
Features
80C51 Core Architecture
256 Bytes of On-chip RAM
1K Bytes of On-chip XRAM
32K Bytes of On-chip Flash Memory
– Data Retention: 10 Years at 85°C
Erase/Write Cycle: 100K
Boot Code Section with Independent Lock Bits
2K Bytes of On-chip Flash for Bootloader
In-System Programming by On-Chip Boot Program (CAN, UART) and IAP Capability
2K Bytes of On-chip EEPROM
Erase/Write Cycle: 100K
14-sources 4-level Interrupts
Three 16-bit Timers/Counters
Full Duplex UART Compatible 80C51
Maximum Crystal Frequency 40 MHz, in X2 Mode, 20 MHz (CPU Core, 20 MHz)
Five Ports: 32 + 2 Digital I/O Lines
Five-channel 16-bit PCA with:
– PWM (8-bit)
– High-speed Output
– Timer and Edge Capture
Double Data Pointer
21-bit Watchdog Timer (7 Programmable Bits)
A 10-bit Resolution Analog to Digital Converter (ADC) with 8 Multiplexed Inputs
Full CAN Controller:
– Fully Compliant with CAN Rev2.0A and 2.0B
– Optimized Structure for Communication Management (Via SFR)
– 15 Independent Message Objects:
Each Message Object Programmable on Transmission or Reception
Individual Tag and Mask Filters up to 29-bit Identifier/Channel
8-byte Cyclic Data Register (FIFO)/Message Object
16-bit Status and Control Register/Message Object
16-bit Time-Stamping Register/Message Object
CAN Specification 2.0 Part A or 2.0 Part B Programmable for Each Message
Object
Access to Message Object Control and Data Registers Via SFR
Programmable Reception Buffer Length Up To 15 Message Objects
Priority Management of Reception of Hits on Several Message Objects at the
Same Time (Basic CAN Feature)
Priority Management for Transmission
Message Object Overrun Interrupt
– Supports:
Time Triggered Communication
Autobaud and Listening Mode
Programmable Automatic Reply Mode
– 1-Mbit/s Maximum Transfer Rate at 8 MHz (1) Crystal Frequency in X2 Mode
– Readable Error Counters
– Programmable Link to On-chip Timer for Time Stamping and Network
Synchronization
– Independent Baud Rate Prescaler
– Data, Remote, Error and Overload Frame Handling
On-chip Emulation Logic (Enhanced Hook System)
Power Saving Modes:
– Idle Mode
– Power-down Mode
1. At BRP = 1 sampling point will be fixed.
Enhanced 8-bit
Microcontroller
with CAN
Controller and
Flash Memory
T89C51CC01
AT89C51CC01
Rev. 4129N–CAN–03/08
1




T89C51CC01 pdf, 반도체, 판매, 대치품
I/O Configurations
Each Port SFR operates via type-D latches, as illustrated in Figure 1 for Ports 3 and 4. A
CPU "write to latch" signal initiates transfer of internal bus data into the type-D latch. A
CPU "read latch" signal transfers the latched Q output onto the internal bus. Similarly, a
"read pin" signal transfers the logical level of the Port pin. Some Port data instructions
activate the "read latch" signal while others activate the "read pin" signal. Latch instruc-
tions are referred to as Read-Modify-Write instructions. Each I/O line may be
independently programmed as input or output.
Port 1, Port 3 and Port 4
Figure 1 shows the structure of Ports 1 and 3, which have internal pull-ups. An external
source can pull the pin low. Each Port pin can be configured either for general-purpose
I/O or for its alternate input output function.
To use a pin for general-purpose output, set or clear the corresponding bit in the Px reg-
ister (x = 1,3 or 4). To use a pin for general-purpose input, set the bit in the Px register.
This turns off the output FET drive.
To configure a pin for its alternate function, set the bit in the Px register. When the latch
is set, the "alternate output function" signal controls the output level (see Figure 1). The
operation of Ports 1, 3 and 4 is discussed further in the "quasi-Bidirectional Port Opera-
tion" section.
Figure 1. Port 1, Port 3 and Port 4 Structure
READ
LATCH
INTERNAL
BUS
WRITE
TO
LATCH
D P1.X Q
P3.X
P4.X
LATCH
CL
ALTERNATE
OUTPUT
FUNCTION
VCC
INTERNAL
PULL-UP (1)
P1.x
P3.x
P4.x
Port 0 and Port 2
READ
PIN
ALTERNATE
INPUT
FUNCTION
Note: The internal pull-up can be disabled on P1 when analog function is selected.
Ports 0 and 2 are used for general-purpose I/O or as the external address/data bus. Port
0, shown in Figure 3, differs from the other Ports in not having internal pull-ups. Figure 3
shows the structure of Port 2. An external source can pull a Port 2 pin low.
To use a pin for general-purpose output, set or clear the corresponding bit in the Px reg-
ister (x = 0 or 2). To use a pin for general-purpose input, set the bit in the Px register to
turn off the output driver FET.
4 A/T89C51CC01
4129N–CAN–03/08

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T89C51CC01 전자부품, 판매, 대치품
A/T89C51CC01
Figure 4. Internal Pull-Up Configurations
2 Osc. PERIODS
OUTPUT DATA
INPUT DATA
READ PIN
VCC VCC
p1(1) p2
VCC
p3
n
P1.x
P2.x
P3.x
P4.x
Note: Port 2 p1 assists the logic-one output for memory bus cycles.
4129N–CAN–03/08
7

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