T89C51AC2 Datasheet PDF - ATMEL Corporation
| Part Number | T89C51AC2 | |
| Description | Enhanced 8-bit Microcontroller | |
| Manufacturers | ATMEL Corporation | |
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Features
• 80C51 Core Architecture
• 256 Bytes of On-chip RAM
• 1 KB of On-chip XRAM
• 32 KB of On-chip Flash Memory
– Data Retention: 10 Years at 85°C
Read/Write Cycle: 10K
• 2 KB of On-chip Flash for Bootloader
• 2 KB of On-chip EEPROM
Read/Write Cycle: 100K
• 14-sources 4-level Interrupts
• Three 16-bit Timers/Counters
• Full Duplex UART Compatible 80C51
• Maximum Crystal Frequency 40 MHz, in X2 Mode, 20 MHz (CPU Core, 20 MHz)
• Five Ports: 32 + 2 Digital I/O Lines
• Five-channel 16-bit PCA with:
– PWM (8-bit)
– High-speed Output
– Timer and Edge Capture
• Double Data Pointer
• 21-bit Watchdog Timer (7 Programmable Bits)
• 10-bit Resolution Analog to Digital Converter (ADC) with 8 Multiplexed Inputs
• On-chip Emulation Logic (Enhanced Hook System)
• Power Saving Modes:
– Idle Mode
– Power-down Mode
• Power Supply: 3V to 5.5V
• Temperature Range: Industrial (-40° to +85°C)
• Packages: VQFP44, PLCC44
Description
The A/T89C51AC2 is a high performance Flash version of the 80C51 single chip 8-bit
microcontrollers. It contains a 32 KB Flash memory block for program and data.
The 32 KB Flash memory can be programmed either in parallel mode or in serial
mode with the ISP capability or with software. The programming voltage is internally
generated from the standard VCC pin.
The A/T89C51AC2 retains all features of the 80C51 with 256 bytes of internal RAM, a
7-source 4-level interrupt controller and three timer/counters. In addition, the
A/T89C51AC2 has a 10-bit A/D converter, a 2 KB Boot Flash memory, 2 KB EEPROM
for data, a Programmable Counter Array, an XRAM of 1024 bytes, a Hardware Watch-
Dog Timer, and a more versatile serial channel that facilitates multiprocessor
communication (EUART). The fully static design of the A/T89C51AC2 reduces system
power consumption by bringing the clock frequency down to any value, even DC,
without loss of data.
The A/T89C51AC2 has two software-selectable modes of reduced activity and an 8-
bit clock prescaler for further reduction in power consumption. In the idle mode the
CPU is frozen while the peripherals and the interrupt system are still operating. In the
Power-down mode the RAM is saved and all other functions are inoperative.
The added features of the A/T89C51AC2 make it more powerful for applications that
need A/D conversion, pulse width modulation, high speed I/O and counting capabili-
ties such as industrial control, consumer goods, alarms, motor control, among others.
While remaining fully compatible with the 80C52, the T8C51AC2 offers a superset of
this standard microcontroller. In X2 mode, a maximum external clock rate of 20 MHz
reaches a 300 ns cycle time.
Enhanced 8-bit
Microcontroller
with 32 KB Flash
Memory
AT89C51AC2
T89C51AC2
Rev. 4127H–8051–02/08
1
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A/T89C51AC2
Table 1. Pin Description (Continued)
Pin Name Type Description
P3.0:7
I/O Port 3:
Is an 8-bit bi-directional I/O port with internal pull-ups. Port 3 pins that have 1’s written to them are pulled high by the internal
pull-up transistors and can be used as inputs in this state. As inputs, Port 3 pins that are being pulled low externally will be a
source of current (IIL, see section "Electrical Characteristic") because of the internal pull-ups.
The output latch corresponding to a secondary function must be programmed to one for that function to operate (except for
TxD and WR). The secondary functions are assigned to the pins of port 3 as follows:
P4.0:1
RESET
ALE
PSEN
EA
XTAL1
XTAL2
P3.0/RxD:
Receiver data input (asynchronous) or data input/output (synchronous) of the serial interface
P3.1/TxD:
Transmitter data output (asynchronous) or clock output (synchronous) of the serial interface
P3.2/INT0:
External interrupt 0 input/timer 0 gate control input
P3.3/INT1:
External interrupt 1 input/timer 1 gate control input
P3.4/T0:
Timer 0 counter input
P3.5/T1:
Timer 1 counter input
P3.6/WR:
External Data Memory write strobe; latches the data byte from port 0 into the external data memory
P3.7/RD:
External Data Memory read strobe; Enables the external data memory.
It can drive CMOS inputs without external pull-ups.
I/O Port 4:
Is an 2-bit bi-directional I/O port with internal pull-ups. Port 4 pins that have 1’s written to them are pulled high by the internal
pull-ups and can be used as inputs in this state. As inputs, Port 4 pins that are being pulled low externally will be a source of
current (IIL, on the datasheet) because of the internal pull-up transistor.
P4.0
P4.1:
It can drive CMOS inputs without external pull-ups.
Reset:
I/O A high level on this pin during two machine cycles while the oscillator is running resets the device. An internal pull-down
resistor to VSS permits power-on reset using only an external capacitor to VCC.
ALE:
O
An Address Latch Enable output for latching the low byte of the address during accesses to the external memory. The ALE is
activated every 1/6 oscillator periods (1/3 in X2 mode) except during an external data memory access. When instructions are
executed from an internal Flash (EA = 1), ALE generation can be disabled by the software.
PSEN:
The Program Store Enable output is a control signal that enables the external program memory of the bus during external
O fetch operations. It is activated twice each machine cycle during fetches from the external program memory. However, when
executing from of the external program memory two activations of PSEN are skipped during each access to the external Data
memory. The PSEN is not activated for internal fetches.
EA:
I When External Access is held at the high level, instructions are fetched from the internal Flash when the program counter is
less then 8000H. When held at the low level,A/T89C51AC2 fetches all instructions from the external program memory.
XTAL1:
I
Input of the inverting oscillator amplifier and input of the internal clock generator circuits.
To drive the device from an external clock source, XTAL1 should be driven, while XTAL2 is left unconnected. To operate
above a frequency of 16 MHz, a duty cycle of 50% should be maintained.
O
XTAL2:
Output from the inverting oscillator amplifier.
4127H–8051–02/08
5
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| Information | Total 30 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
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