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부품번호 | MC74VHC1GT126 기능 |
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기능 | Noninverting Buffer / CMOS Logic Level Shifter | ||
제조업체 | ON Semiconductor | ||
로고 | |||
전체 8 페이지수
MC74VHC1GT126
Noninverting Buffer /
CMOS Logic Level Shifter
with LSTTL−Compatible Inputs
The MC74VHC1GT126 is a single gate noninverting 3−state buffer
fabricated with silicon gate CMOS technology. It achieves high speed
operation similar to equivalent Bipolar Schottky TTL while maintaining
CMOS low power dissipation.
The MC74VHC1GT126 requires the 3−state control input (OE) to be
set Low to place the output into the high impedance state.
The device input is compatible with TTL−type input thresholds and the
output has a full 5 V CMOS level output swing. The input protection
circuitry on this device allows overvoltage tolerance on the input,
allowing the device to be used as a logic−level translator from 3.0 V
CMOS logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic to 3.0 V
CMOS Logic while operating at the high−voltage power supply.
The MC74VHC1GT126 input structure provides protection when
voltages up to 7V are applied, regardless of the supply voltage. This
allows the MC74VHC1GT126 to be used to interface 5 V circuits to 3 V
circuits. The output structures also provide protection when VCC = 0 V.
These input and output structures help prevent device destruction caused
by supply voltage − input/output voltage mismatch, battery backup, hot
insertion, etc.
• High Speed: tPD = 3.5 ns (Typ) at VCC = 5 V
• Low Power Dissipation: ICC = 1 mA (Max) at TA = 25°C
• TTL−Compatible Inputs: VIL = 0.8 V; VIH = 2.0 V
• CMOS−Compatible Outputs: VOH > 0.8 VCC; VOL < 0.1 VCC @Load
• Power Down Protection Provided on Inputs and Outputs
• Balanced Propagation Delays
• Pin and Function Compatible with Other Standard Logic Families
• Chip Complexity: FETs = 62; Equivalent Gates = 16
OE 1
IN A 2
GND 3
5 VCC
4 OUT Y
http://onsemi.com
MARKING
DIAGRAMS
SC−88A / SOT−353/SC−70
DF SUFFIX
CASE 419A
W3d
Pin 1
d = Date Code
TSOP−5/SOT−23/SC−59
DT SUFFIX
CASE 483
W3d
Pin 1
d = Date Code
PIN ASSIGNMENT
1 OE
2 IN A
3 GND
4 OUT Y
5 VCC
A Input
L
H
X
FUNCTION TABLE
OE Input
Y Output
HL
HH
LZ
Figure 1. Pinout (Top View)
OE
OUT Y
IN A
Figure 2. Logic Symbol
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
© Semiconductor Components Industries, LLC, 2002
December, 2003 − Rev. 9
1
Publication Order Number:
MC74VHC1GT126/D
MC74VHC1GT126
SWITCHING WAVEFORMS
A
tPLH
50%
50% VCC
Y
VCC
GND
tPHL
Figure 4. Switching Waveforms
OE 50%
tPZL tPLZ
Y 50% VCC
tPZH tPHZ
Y 50% VCC
Figure 5.
VCC
GND
HIGH
IMPEDANCE
VOL + 0.3V
VOH − 0.3V
HIGH
IMPEDANCE
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
CL*
DEVICE
UNDER
TEST
TEST POINT
OUTPUT 1 kW
CL *
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.
*Includes all probe and jig capacitance
Figure 6. Test Circuit
*Includes all probe and jig capacitance
Figure 7. Test Circuit
INPUT
Figure 8. Input Equivalent Circuit
DEVICE ORDERING INFORMATION
Device Nomenclature
Device
Order Number
Temp
Circuit Range
Device Package
Indicator Identifier Technology Function Suffix
Tape &
Reel
Suffix
Package Type
(Name/SOT#/
Common Name)
Tape and
Reel Size†
MC74VHC1GT126DF1 MC
74
VHC1G
T126
DF
SC−88A / SOT−353 178 mm (7”)
1
/ SC−70
3000 Unit
MC74VHC1GT126DF2 MC
74
VHC1G
T126
DF
SC−88A / SOT−353 178 mm (7”)
2
/ SC−70
3000 Unit
MC74VHC1GT126DT1 MC
74
VHC1G
T126
DT
TSOP5 / SOT−23 178 mm (7”)
1
/ SC−59
3000 Unit
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
http://onsemi.com
4
4페이지 MC74VHC1GT126
PACKAGE DIMENSIONS
A
G
SC70−5/SC−88A/SOT−353
DF SUFFIX
5−LEAD PACKAGE
CASE 419A−02
ISSUE G
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. 419A−01 OBSOLETE. NEW STANDARD
419A−02.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
54
S −B−
12
3
D 5 PL
0.2 (0.008) M B M
N
INCHES
DIM MIN MAX
A 0.071 0.087
B 0.045 0.053
C 0.031 0.043
D 0.004 0.012
G 0.026 BSC
H −−− 0.004
J 0.004 0.010
K 0.004 0.012
N 0.008 REF
S 0.079 0.087
MILLIMETERS
MIN MAX
1.80 2.20
1.15 1.35
0.80 1.10
0.10 0.30
0.65 BSC
−−− 0.10
0.10 0.25
0.10 0.30
0.20 REF
2.00 2.20
J
K
SOLDERING FOOTPRINT*
0.50
0.0197
0.65
0.025
0.40
0.0157
0.65
0.025
1.9
0.0748
ǒ ǓSCALE 20:1
mm
inches
Figure 14. SC−88A/SC70−5/SOT−353
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
7
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부품번호 | 상세설명 및 기능 | 제조사 |
MC74VHC1GT125 | Noninverting Buffer / CMOS Logic Level Shifter | ON Semiconductor |
MC74VHC1GT126 | Noninverting Buffer / CMOS Logic Level Shifter | ON Semiconductor |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |