PDF MC74VHCT540A Data sheet ( Hoja de datos )

Número de pieza	MC74VHCT540A
Descripción	Octal Bus Buffer Inverting
Fabricantes	Motorola Semiconductors
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No Preview Available ! MOTOROLA SEMICONDUCTOR TECHNICAL DATA Octal Bus Buffer Inverting The MC74VHCT540A is an advanced high speed CMOS inverting octal bus buffer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. The MC74VHCT540A features inputs and outputs on opposite sides of the package and two AND–ed active–low output enables. When either OE1 or OE2 are high, the terminal outputs are in the high impedance state. The VHCT inputs are compatible with TTL levels. This device can be used as a level converter for interfacing 3.3V to 5.0V, because it has full 5V CMOS level output swings. The VHCT540A input and output (when disabled) structures provide protection when voltages between 0V and 5.5V are applied, regardless of the supply voltage. These input and output structures help prevent device destruction caused by supply voltage – input/output voltage mismatch, battery backup, hot insertion, etc. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to 7V, allowing the interface of 5V systems to 3V systems. • High Speed: tPD = 3.7ns (Typ) at VCC = 5V • Low Power Dissipation: ICC = 4µA (Max) at TA = 25°C • TTL–Compatible Inputs: VIL = 0.8V; VIH = 2.0V • Power Down Protection Provided on Inputs • Balanced Propagation Delays • Designed for 2V to 5.5V Operating Range • Low Noise: VOLP = 1.2V (Max) • Pin and Function Compatible with Other Standard Logic Families • Latchup Performance Exceeds 300mA • ESD Performance: HBM > 2000V; Machine Model > 200V • Chip Complexity: 124 FETs or 31 Equivalent Gates DATA INPUTS OUTPUT ENABLES 2 A1 3 A2 4 A3 5 A4 6 A5 7 A6 8 A7 9 A8 OE1 1 OE2 19 LOGIC DIAGRAM 18 Y1 17 Y2 16 Y3 15 Y4 14 Y5 INVERTING OUTPUTS 13 Y6 12 Y7 11 Y8 MC74VHCT540A DW SUFFIX 20–LEAD SOIC WIDE PACKAGE CASE 751D–05 DT SUFFIX 20–LEAD TSSOP PACKAGE CASE 948E–02 M SUFFIX 20–LEAD SOIC EIAJ PACKAGE CASE 967–01 ORDERING INFORMATION MC74VHCTXXXADW SOIC WIDE MC74VHCTXXXADT TSSOP MC74VHCTXXXAM SOIC EIAJ PIN ASSIGNMENT OE1 1 A1 2 A2 3 A3 4 A4 5 A5 6 A6 7 A7 8 A8 9 GND 10 20 VCC 19 OE2 18 Y1 17 Y2 16 Y3 15 Y4 14 Y5 13 Y6 12 Y7 11 Y8 FUNCTION TABLE Inputs OE1 OE2 A LLL L LH HXX XHX Output Y H L Z Z 4/99 © Motorola, Inc. 1999 1 REV 0 1 page MC74VHCT540A OUTLINE DIMENSIONS DW SUFFIX PLASTIC SOIC WIDE PACKAGE CASE 751D–05 ISSUE F D A q 20 11 E 1 10 NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. 20X B B 0.25 M T A S B S 18X e A SEATING PLANE A1 T C MILLIMETERS DIM MIN MAX A 2.35 2.65 A1 0.10 0.25 B 0.35 0.49 C 0.23 0.32 D 12.65 12.95 E 7.40 7.60 e 1.27 BSC H 10.05 10.55 h 0.25 0.75 L 0.50 0.90 q 0_ 7_ VHC Data – Advanced CMOS Logic DL203 — Rev 2 5 MOTOROLA 5 Page

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