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PDF MC74VHCT32A Data sheet ( Hoja de datos )

Número de pieza MC74VHCT32A
Descripción QUAD 2 INPUT OR GATE CMOS LOGIC LEVEL SHIFTER
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MC74VHCT32A
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Quad 2-Input OR Gate /
CMOS Logic Level Shifter
with LSTTL–Compatible Inputs
The MC74VHCT32A is an advanced high speed CMOS 2–input
OR gate fabricated with silicon gate CMOS technology. It achieves
high speed operation similar to equivalent Bipolar Schottky TTL
while maintaining CMOS low power dissipation.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output.
The device input is compatible with TTL–type input thresholds and
the output has a full 5V CMOS level output swing. The input
protection circuitry on this device allows overvoltage tolerance on the
input, allowing the device to be used as a logic–level translator from
3.0V CMOS logic to 5.0V CMOS Logic or from 1.8V CMOS logic to
3.0V CMOS Logic while operating at the high–voltage power supply.
The MC74VHCT32A input structure provides protection when
voltages up to 7V are applied, regardless of the supply voltage. This
allows the MC74VHCT32A to be used to interface 5V circuits to 3V
circuits. The output structures also provide protection when VCC = 0V.
These input and output structures help prevent device destruction
caused by supply voltage – input/output voltage mismatch, battery
backup, hot insertion, etc.
High Speed: tPD = 3.8ns (Typ) at VCC = 5V
Low Power Dissipation: ICC = 2µA (Max) at TA = 25°C
TTL–Compatible Inputs: VIL = 0.8V; VIH = 2.0V
Power Down Protection Provided on Inputs
Balanced Propagation Delays
Designed for 2V to 5.5V Operating Range
Low Noise: VOLP = 0.8V (Max)
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300mA
ESD Performance: HBM > 2000V; Machine Model > 200V
LOGIC DIAGRAM
1
A1
2
B1
4
A2
B2 5
9
A3
B3 10
3
Y1
6
Y2
)Y = A B
8
Y3
A4 12
13
B4
11
Y4
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
© Semiconductor Components Industries, LLC, 1999
October, 1999 – Rev. 0.0
1
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14–LEAD SOIC
D SUFFIX
CASE 751A
14–LEAD TSSOP
DT SUFFIX
CASE 948G
14–LEAD SOIC EIAJ
M SUFFIX
CASE 965
PIN CONNECTION AND
MARKING DIAGRAM (Top View)
VCC B4 A4 Y4 B3 A3 Y3
14 13 12 11 10 9 8
1234567
A1 B1 Y1 A2 B2 Y2 GND
For detailed package marking information, see the Marking
Diagram section on page 4 of this data sheet.
FUNCTION TABLE
Inputs
Output
AB
Y
LL
LH
HL
HH
L
H
H
H
ORDERING INFORMATION
Device
Package
Shipping
MC74VHCT32AD
SOIC
55 Units/Rail
MC74VHCT32ADT TSSOP
96 Units/Rail
MC74VHCT32AM SOIC EIAJ 50 Units/Rail
Publication Order Number:
MC74VHCT32A/D

1 page




MC74VHCT32A pdf
MC74VHCT32A
PACKAGE DIMENSIONS
0.15 (0.006) T U S
2X L/2 14
L
PIN 1
IDENT.
1
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948G–01
ISSUE O
14X K REF
0.10 (0.004) M T U S V S
8
B
–U–
7
N 0.25 (0.010)
M
N
F
DETAIL E
0.15 (0.006) T U S
A
–V–
K
J J1 ÇÇÉÉÇÇKÉÉÇÇ1
SECTION N–N
0.10 (0.004)
–T– SEATING
PLANE
D
C
G
H DETAIL E
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE –W–.
–W–
MILLIMETERS
INCHES
DIM MIN MAX MIN MAX
A 4.90 5.10 0.193 0.200
B 4.30 4.50 0.169 0.177
C ––– 1.20 ––– 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
G 0.65 BSC
0.026 BSC
H 0.50 0.60 0.020 0.024
J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K 0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L 6.40 BSC
0.252 BSC
M 0_ 8_ 0_ 8_
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