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PDF MC74VHC1G50 Data sheet ( Hoja de datos )
| Número de pieza | MC74VHC1G50 | |
| Descripción | Buffer | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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MC74VHC1G50
Product Preview
Buffer
The MC74VHC1G50 is an advanced high speed CMOS buffer
fabricated with silicon gate CMOS technology. It achieves high speed
operation similar to equivalent Bipolar Schottky TTL while
maintaining CMOS low power dissipation.
The internal circuit is composed of three stages, including a buffered
output which provides high noise immunity and stable output.
The MC74VHC1G50 input structure provides protection when
voltages up to 7V are applied, regardless of the supply voltage. This
allows the MC74VHC1G50 to be used to interface 5V circuits to 3V
circuits.
• High Speed: tPD = 3.5ns (Typ) at VCC = 5V
• Low Power Dissipation: ICC = 2µA (Max) at TA = 25°C
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300mA
• ESD Performance: HBM > 1500V; MM > 200V
NC 1
IN A 2
GND 3
5 VCC
4 OUT Y
http://onsemi.com
SC–88A / SOT–353
DF SUFFIX
CASE 419A
MARKING DIAGRAM
VRd
Pin 1
d = Date Code
PIN ASSIGNMENT
1 NC
2 IN A
3 GND
4 OUT Y
5 VCC
Figure 1. 5–Lead SOT–353 Pinout (Top View)
LOGIC SYMBOL
IN A 1 OUT Y
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
FUNCTION TABLE
A Input
L
H
Y Output
L
H
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
© Semiconductor Components Industries, LLC, 1999
February, 2000 – Rev. 0
1
Publication Order Number:
MC74VHC1G50/D
1 page  
K
t
TOP
COVER
TAPE
B1 K0
SEE
NOTE 2
FOR MACHINE REFERENCE
ONLY
INCLUDING DRAFT AND RADII
CONCENTRIC AROUND B0
MC74VHC1G50
10 PITCHES
CUMULATIVE
TOLERANCE ON
P0
TAPE
±0.2 mm
D P2 (±0.008”)
E
A0 SEE NOTE 2
+ B0
+
P
EMBOSSMENT
USER DIRECTION OF FEED
FW
+
CENTER LINES
OF CAVITY
D1
FOR COMPONENTS
2.0 mm × 1.2 mm
AND LARGER
BENDING RADIUS
R MIN.
TAPE AND COMPONENTS
SHALL PASS AROUND RADIUS “R”
WITHOUT DAMAGE
EMBOSSED
CARRIER
*TOP COVER
TAPE THICKNESS (t1)
0.10 mm
(0.004”) MAX.
EMBOSSMENT
MAXIMUM COMPONENT ROTATION
10°
TYPICAL
COMPONENT CAVITY
CENTER LINE
100 mm
(3.937”)
1 mm MAX
TAPE
TYPICAL
COMPONENT
CENTER LINE
1 mm
250 mm
(0.039”) MAX (9.843”)
CAMBER (TOP VIEW)
ALLOWABLE CAMBER TO BE 1 mm/100 mm NONACCUMULATIVE OVER 250 mm
Figure 4. Carrier Tape Specifications
EMBOSSED CARRIER DIMENSIONS (See Notes 1 and 2)
Tape B1
Size Max
D
D1
E
F
K
P
P0 P2 R
T
W
8 mm 4.35 mm
(0.171”)
1.5 +0.1/
–0.0 mm
(0.059
+0.004/
–0.0”)
1.0 mm
Min
(0.039”)
1.75
±0.1 mm
(0.069
±0.004”)
3.5
±0.5 mm
(1.38
±0.002”)
2.4 mm
(0.094”)
4.0
±0.10 mm
(0.157
±0.004”)
4.0
±0.1 mm
(0.156
±0.004”)
2.0
±0.1 mm
(0.079
±0.002”)
25 mm
(0.98”)
0.3
±0.05 mm
(0.01
+0.0038/
–0.0002”)
8.0
±0.3 mm
(0.315
±0.012”)
1. Metric Dimensions Govern–English are in parentheses for reference only.
2. A0, B0, and K0 are determined by component size. The clearance between the components and the cavity must be within 0.05 mm min to
0.50 mm max. The component cannot rotate more than 10° within the determined cavity
http://onsemi.com
5
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| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet MC74VHC1G50.PDF ] | |
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