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PDF TNT4882 Data sheet ( Hoja de datos )
| Número de pieza | TNT4882 | |
| Descripción | Single-Chip IEEE 488.2 Talker / Listener ASIC | |
| Fabricantes | National Instruments | |
| Logotipo |  |
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TNT4882
Single-Chip IEEE 488.2 Talker/Listener ASIC
Features
100-pin plastic quad flat pack (QFP), surface-
mount package
IEEE 488.1-compatible transceivers on chip
Fast data transfers
– Up to 1.5 Mbytes/s using interlocked
IEEE 488.1 handshake
– Up to 8 Mbytes/s using HS488™
Two 8-bit 16-deep FIFOs buffer data
between GPIB and CPU
With exception of Controller, performs all
IEEE 488 interface functions
– SH1, AH1, T5 or TE5, L3 or LE3,
SR1, RL1, PP1 or PP2, DC1, DT1,
and C0
Meets all IEEE 488.2 requirements
– Bus line monitoring
– Preferred implementation of
requesting service
– Not sending messages when there are
no Listeners
Software compatible with
Turbo488™/NAT4882™ ASICs
Reduces software overhead
– Does not lose a data byte if ATN is
asserted while transmitting data
– Static interrupts status bits that do
not clear when read
– Automatically transmits END or
performs RFD holdoff on last byte
of DMA transfer
– Interrupts when handshake is
complete on last byte of a DMA
transfer
– Has 32-bit counter for large,
uninterrupted data transfers
Programmable timer interrupt for
general-purpose timing use
Complete in-system functional testing
with internal loop-back mode
ISA bus glue logic on chip
Direct memory access (DMA)
Device status indicator pins
– My Address, Talk Addressed, Listen
Addressed, REM, DCAS, TRIG
Automatically processes IEEE 488
commands and reads undefined
commands
Handles 6 primary and secondary
addressing modes
Automatic EOS and/or NL message
detection
Programmable data transfer rate –
TTL-compatible CMOS device
NEW!
Description
The TNT4882 provides a single-chip IEEE 488.2 Talker/Listener
interface to the general-purpose interface bus (GPIB). The
TNT4882 combines the circuitry of the NAT4882 IEEE 488.2
application-specific integrated circuit (ASIC), Turbo488
performance-enhancing ASIC, and GPIB transceivers to create a
single-chip IEEE 488.2 interface. Because the TNT4882 contains
the NAT4882 register set, which in turn has the NEC µPD7210
and TI TMS 9914A register sets, developers using any of these
chips can easily port existing code directly to the TNT4882,
thereby significantly reducing software development time. Also,
with just a few modifications, you can implement all the
improved features of the IEEE 488.2 standard. The TNT4882 is
ideal for use in all IEEE 488 instrument designs because of its
small size, surface-mount ability, and performance
enhancements that include HS488, a new high-speed mode for
GPIB transfers.
HS488 Overview
The HS488 high-speed mode for GPIB transfers increases the
maximum data transfer rate of devices on a GPIB network up to
8 Mbytes/s. The TNT4882 completely and transparently handles
the HS488 protocol without additional circuitry, a method that is
a superset of the IEEE 488 standard. Thus, you can mix existing
GPIB devices with HS488 devices without changing your
application programs. The TNT4882 can implement high-speed
data transfers automatically. Maximum data transfer rates
obtainable using HS488 depend on the host architecture and
system configuration.
Architecture, Modes
The TNT4882 integrates the circuitry of the Turbo488, NAT4882,
and IEEE 488.1- compatible transceivers. The TNT4882 circuitry
logically interconnects these three components in one of two
ways – “one-chip mode” (see Figure 1) or “two-chip mode”
(see Figure 2).
The TNT4882 powers up in two-chip mode, which exactly
duplicates the Turbo488/NAT4882 chipset for software
compatibility. During I/O accesses in two-chip mode, the CPU
accesses the Turbo488 and passes all accesses within a certain
address range to the NAT4882. The Turbo488 also manages
transfers between its internal first-in first-out buffers (FIFOs) and
the NAT4882, arbitrating between these data transfers and any
I/O accesses of the NAT4882 by the CPU. Accesses to the
NAT4882 registers take longer than Turbo488 accesses because
all accesses to the NAT4882 registers must go through the
Turbo488 and its arbiter.
To achieve higher data transfer rates, you can switch the
TNT4882 to one-chip mode in software. In one-chip mode, the
first-in first-out (FIFO) buffer connects directly to the GPIB
transceivers and the CPU accesses all registers directly. You can
access NAT4882 registers in the same amount of time as
Turbo488 registers because accesses to these registers do not go
through the Turbo488.
The NAT4882 portion of the TNT4882 can emulate either the
NEC µPD7210 or the TI TMS9914A GPIB controller chips. The
state of one of the TNT4882 input pins determines the chip
emulation mode on power up, but you can switch the chip
emulation mode back and forth between 7210 and 9914
modes through software.
340570D-01
030599
1 page  
TNT4882
Single-Chip IEEE 488.2 Talker/Listener ASIC
ISA Pin Description
All input (I) and bidirectional (I/O) pins have an internal pull-up resistor between 50 kΩ and 150 kΩ. Pins with names that end in “N” are
active low signals – all others are active high. Open-collector outputs are type “OC.”
Note: You can also see the “Hardware Considerations” chapter of the “TNT Programmer Reference Manual” (P/N 320724-01) for more
information.
Pin No.(s)
1
2,3,5,6,7,9,10,11
Name(s)
D7_0_OEN
DATA15-8
14
19-15
31,30,29,28,26
20
21,54
52,51,23,22,55
32
33
34
37
38
BHEN_N
ADDR4-0
ADDR9-5
D15_8_OEN
NC
SW9-5
DRQ
DACKN
INTR
AEN_N
IOCHRDY
50,49,47,46,44,
43,42,39
DATA7-0
53 MODE
62 SENSE_8_16N
63 IORN
64 IOWN
66
67
71,74,77,80,88,
89,91,92
70,73,76,79,81,
82,84,85
95
96
98
99
100
4,8,13,25,27,35,41,
45,48,57,61,65,68,72,
75,78,83,86,90,93,97
12,24,36,40,56,58,
59,60,69,87,94
IOCS16N
RESET
DIO8-1N
RENN, ATNN, SRQN,
IFCN, NDACN, NRFDN,
DAVN, EOIN
XTAL0
XTAL1
KEYCLKN
KEYDQ
KEYRSTN
GND
VDD
Type Description
O Asserts when DATA7-0 bus is enabled for output – may be left unconnected
I/O Upper eight bits of bidirectional three-state data bus for transfer of commands,
data, and status between TNT4882 and CPU – can connect directly to the AT bus –
DATA15 is the most significant bit
I Enables access to upper eight bits of data bus when asserted
I Determines which register will be accessed during an I/O access
I Determines if an I/O address is within the range occupied by the TNT4882 –
the chip is selected and an I/O access occurs when ADDR9-5 match SW9-5 and
AEN_N is asserted
O Asserts when DATA15:8 bus is enabled for output – may be left unconnected
O Leave unconnected
I Determines the base address of the TNT4882
O Asserts to request a DMA transfer cycle
I Enables FIFO accesses during a DMA transfer cycle
O Asserts when one or more of the unmasked interrupt conditions becomes true
I Enables I/O accesses to the TNT4882
OC When the TNT4882 is not accessed, this open-collector signal is not driven, and a
pull-up resistor on the system board keeps it pulled high – at the start of some
TNT4882 accesses, the TNT4882 may drive it low, then pull it high again during the
cycle to indicate that the TNT4882 is ready for the CPU to end that cycle
I/O Lower eight bits of bidirectional three-state data bus for transfer of commands, data,
and status between TNT4882 and CPU – can connect directly to the AT bus – DATA7
is the most significant bit
I Forces the TNT4882 to 7210 (high) or 9914 (low) emulation mode on a hardware
reset – may be left unconnected
I Pull this pin low to tell the TNT4882 that it is connected to a 16-bit bus – leave it
unconnected if the TNT4882 is connected to an 8-bit bus
I Drives the contents of the register selected by ADDR4-0 on the data bus when the
TNT4882 is selected
I The value on the data bus is latched into the register selected by ADDR4-0 on the
rising edge of IOWN when you select the TNT4882
OC Driven low during an access to the upper data bus
I Causes a hardware reset and holds the TNT4882 in its idle state while asserted
I/O 8-bit bidirectional IEEE 488 data bus
I/O IEEE 488 control signals
O Output of crystal circuit – use only for driving a quartz crystal
I Crystal oscillator input – drive with a 40 MHz CMOS input level clock signal
O Strobes data to or from the DS1204 electronic key
I/O Transmits serial data between the TNT4882 and a DS1204 key
O Resets a DS1204 key
– Ground pins – 0 V
– Power pins – +5 V (±5%)
National Instruments
Phone: (512) 794-0100 • Fax: (512) 683-9300 • [email protected] • www.natinst.com
5
5 Page 
TNT4882
Single-Chip IEEE 488.2 Talker/Listener ASIC
Generic Mode AC Characteristics Waveforms
ABUSN,
BBUSN,
ADDR4-0
CSN
RDN
t
AS
t
CS
DATA
RDY1
CPUACC††
†† CPUACC asserts during two-chip mode
NAT4882 accesses only
t
RD
t
ARDY
t
CPU
t
RW
Figure 7. CPU Read
DRQ
DACKN
RDN
DATA15-0
RDY1
t
DU
t
DS
t
RP
t
DR
t
RDYQ
t
AH
t
CH
t
DF
t
URDY
t
CPU
t
DH
t
DF
t
URDY
Figure 8. DMA Read
ABUSN,
BBUSN,
ADDR4-0
CSN
WRN
DATA
tAS
tCS
tWP
tWS
RDY1
CPUACC††
†† CPUACC asserts during two-chip mode
NAT4882 accesses only
tARDY
tCPU
Figure 9. CPU Write
tAH
tCH
tWH
tURDY
tCPU
Waveforms continued on page 12
National Instruments 11
Phone: (512) 794-0100 • Fax: (512) 683-9300 • [email protected] • www.natinst.com
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet TNT4882.PDF ] | |
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