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부품번호 | 82865G 기능 |
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기능 | Graphics and Memory Controller Hub | ||
제조업체 | Intel | ||
로고 | |||
전체 30 페이지수
Intel® 865G/865GV Chipset
Datasheet
Intel® 82865G/82865GV Graphics and Memory Controller Hub
(GMCH)
February 2004
Document Number: 252514-005
3.4 I/O Mapped Registers.................................................................................... 52
3.4.1 CONFIG_ADDRESS—Configuration Address Register ................... 53
3.4.2 CONFIG_DATA—Configuration Data Register ................................ 54
3.5 DRAM Controller/Host-Hub Interface Device Registers (Device 0) ............... 55
3.5.1 VID—Vendor Identification Register (Device 0)................................ 57
3.5.2 DID—Device Identification Register (Device 0) ................................ 57
3.5.3 PCICMD—PCI Command Register (Device 0)................................. 58
3.5.4 PCISTS—PCI Status Register (Device 0) ........................................ 59
3.5.5 RID—Revision Identification Register (Device 0) ............................. 60
3.5.6 SUBC—Sub-Class Code Register (Device 0) .................................. 60
3.5.7 BCC—Base Class Code Register (Device 0) ................................... 60
3.5.8 MLT—Master Latency Timer Register (Device 0)............................. 61
3.5.9 HDR—Header Type Register (Device 0) .......................................... 61
3.5.10 APBASE—Aperture Base Configuration Register (Device 0)........... 62
3.5.11 SVID—Subsystem Vendor Identification Register (Device 0)........... 63
3.5.12 SID—Subsystem Identification Register (Device 0).......................... 63
3.5.13 CAPPTR—Capabilities Pointer Register (Device 0) ......................... 63
3.5.14 AGPM—AGP Miscellaneous Configuration Register
(Device 0) ......................................................................................... 64
3.5.15 GC—Graphics Control Register (Device 0) ...................................... 65
3.5.16 CSABCONT—CSA Basic Control Register (Device 0)..................... 67
3.5.17 FPLLCONT— Front Side Bus PLL Clock Control Register
(Device 0) ......................................................................................... 68
3.5.18 PAM[0:6]—Programmable Attribute Map Registers
(Device 0) ......................................................................................... 69
3.5.19 FDHC—Fixed Memory(ISA) Hole Control Register
(Device 0) ......................................................................................... 71
3.5.20 SMRAM—System Management RAM Control Register
(Device 0) ......................................................................................... 72
3.5.21 ESMRAMC—Extended System Management RAM Control
(Device 0) ......................................................................................... 73
3.5.22 ACAPID—AGP Capability Identifier Register (Device 0) .................. 74
3.5.23 AGPSTAT—AGP Status Register (Device 0) ................................... 74
3.5.24 AGPCMD—AGP Command Register (Device 0).............................. 76
3.5.25 AGPCTRL—AGP Control Register (Device 0) ................................. 77
3.5.26 APSIZE—Aperture Size Register (Device 0) .................................... 78
3.5.27 ATTBASE—Aperture Translation Table Register (Device 0)............ 78
3.5.28 AMTT—AGP MTT Control Register (Device 0) ................................ 79
3.5.29 LPTT—AGP Low Priority Transaction Timer Register
(Device 0) ......................................................................................... 80
3.5.30 TOUD—Top of Used DRAM Register (Device 0) ............................. 81
3.5.31 GMCHCFG—GMCH Configuration Register (Device 0)................... 82
3.5.32 ERRSTS—Error Status Register (Device 0)..................................... 84
3.5.33 ERRCMD—Error Command Register (Device 0) ............................. 85
3.5.34 SKPD—Scratchpad Data Register (Device 0) .................................. 86
3.5.35 CAPREG—Capability Identification Register (Device 0) .................. 86
3.6 PCI-to-AGP Bridge Configuration Register (Device 1) .................................. 87
3.6.1 VID1—Vendor Identification Register (Device 1).............................. 88
3.6.2 DID1—Device Identification Register (Device 1) .............................. 88
3.6.3 PCICMD1—PCI Command Register (Device 1)............................... 89
3.6.4 PCISTS1—PCI Status Register (Device 1) ...................................... 90
3.6.5 RID1—Revision Identification Register (Device 1) ........................... 91
4 Intel® 82865G/82865GV GMCH Datasheet
4페이지 4.4 AGP Memory Address Ranges....................................................................146
5 Functional Description ...................................................................................147
5.1 Processor Front Side Bus (FSB)..................................................................147
5.1.1 FSB Dynamic Bus Inversion ...........................................................147
5.1.2 FSB Interrupt Overview...................................................................148
5.1.2.1 Upstream Interrupt Messages .........................................148
5.2 System Memory Controller ..........................................................................149
5.2.1 DRAM Technologies and Organization...........................................150
5.2.2 Memory Operating Modes ..............................................................150
5.2.2.1 Dynamic Addressing Mode..............................................151
5.2.3 Single-Channel (SC) Mode .............................................................151
5.2.3.1 Linear Mode.....................................................................151
5.2.3.2 Tiled Mode.......................................................................151
5.2.4 Memory Address Translation and Decoding ...................................151
5.2.5 Memory Organization and Configuration ........................................156
5.2.6 Configuration Mechanism for DIMMS .............................................157
5.2.6.1 Memory Detection and Initialization.................................157
5.2.6.2 SMBus Configuration and Access of the Serial Presence
Detect Ports.....................................................................157
5.2.6.3 Memory Register Programming.......................................157
5.2.7 Memory Thermal Management.......................................................158
5.2.7.1 Determining When to Thermal Manage...........................158
5.3 Accelerated Graphics Port (AGP) ................................................................158
5.3.1 GMCH AGP Support.......................................................................159
5.3.2 Selecting between AGP 3.0 and AGP 2.0 ......................................159
5.3.3 AGP 3.0 Downshift (4X Data Rate) Mode.......................................159
5.3.3.1 Mechanism for Detecting AGP 2.0, AGP 3.0, or
Intel® DVO.......................................................................160
5.3.4 AGP Target Operations ..................................................................162
5.3.5 AGP Transaction Ordering..............................................................162
5.3.6 Support for PCI-66 Devices ............................................................163
5.3.7 8X AGP Protocol.............................................................................163
5.3.7.1 Fast Writes ......................................................................163
5.3.7.2 PCI Semantic Transactions on AGP ...............................163
5.4 Integrated Graphics Controller.....................................................................164
5.4.1 3D Engine .......................................................................................165
5.4.1.1 Setup Engine ...................................................................165
5.4.1.2 Scan Converter................................................................166
5.4.1.3 2D Functionality...............................................................166
5.4.1.4 Texture Engine ................................................................166
5.4.1.5 Raster Engine..................................................................168
5.4.2 2D Engine .......................................................................................172
5.4.3 Video Engine...................................................................................173
5.4.4 Planes .............................................................................................173
5.4.4.1 Cursor Plane....................................................................173
5.4.4.2 Overlay Plane ..................................................................174
5.4.5 Pipes ...............................................................................................175
5.5 Display Interfaces ........................................................................................175
5.5.1 Analog Display Port Characteristics................................................176
5.5.2 Digital Display Interface ..................................................................177
5.5.2.1 Digital Display Channels – Intel® DVOB and Intel® DVOC ...
177
Intel® 82865G/82865GV GMCH Datasheet
7
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부품번호 | 상세설명 및 기능 | 제조사 |
82865G | Graphics and Memory Controller Hub | Intel |
82865GV | Graphics and Memory Controller Hub | Intel |
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