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S3067 데이터시트 PDF




Applied Micro Circuits에서 제조한 전자 부품 S3067은 전자 산업 및 응용 분야에서
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부품번호 S3067 기능
기능 Multirate Sonet / SDH / ATM Transceiver w/FEC
제조업체 Applied Micro Circuits
로고 Applied Micro Circuits 로고


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S3067 데이터시트, 핀배열, 회로
DEVICE
SMPUELCTIFIIRCAATTIEON(OC-48/24/12/3/GBE/FC) SONET/SDH/ATM TRANSCEIVER w/ FEC
SMBOUiCNLMETIOTR/SASDTLEHVP/(AOETCCM-L48OC/C2L4-O1/1C22K/3T/GRGEABNEES/FRMCAI)TTSTOOERNREATN/SDDRHE/ACTEMIVTERRANSCEIVER w/ FEC
®
S3067
SS33006677
FEATURES
• SiGe BiCMOS technology
• Complies with Bellcore and ITU-T
specifications
• On-chip high-frequency PLL for clock generation
• Supports:
- OC-48 (with FEC)
- OC-24 (with FEC)
- OC-12 (with FEC)
- OC-3 (with FEC)
- Fibre Channel
• FEC capability up to 8 bytes per 255-byte block
• Reference frequency – 131.25 MHz to 178 MHz
• Interface to LVPECL and TTL logic
• 16-Bit single-ended LVPECL data path
• Compact 156 Pin TBGA package
• Diagnostic loopback mode
• Supports line timing
• Lock Detect
• Signal detect input
• Low jitter LVPECL interface
• Internal FIFO to decouple transmit clocks
• Single 3.3 V supply
• Typical power 1.5 W
APPLICATIONS
• Wavelength Division Multiplexing equipment
• SONET/SDH-based transmission systems
• SONET/SDH modules
• SONET/SDH test equipment
• ATM over SONET/SDH
• Section repeaters
• Add Drop Multiplexers (ADM)
• Broad-band cross-connects
• Fiber optic terminators
• Fiber optic test equipment
GENERAL DESCRIPTION
The S3067 SONET/SDH transceiver chip is a fully
integrated multirate serialization/deserialization SO-
NET OC-48, OC-24, OC-12 and OC-3 interface
device. The chip performs all necessary serial-to-
parallel and parallel-to-serial functions in
conformance with SONET/SDH transmission and
Forward Error Correction (FEC) standards. The de-
vice is suitable for SONET-based WDM applications.
Figure 1 shows a typical network application.
On-chip clock synthesis is performed by the high-
frequency phase-locked loop on the S3067
transceiver chip allowing the use of a slower external
transmit clock reference. The chip can be used with a
131.25 MHz to 178 MHz reference clock in support
of existing system clocking schemes.
The low jitter LVPECL interface guarantees compli-
ance with the bit-error rate requirements of the
Bellcore and ITU-T standards. The S3067 is pack-
aged in a 156 Pin TBGA, offering designers a small
package outline.
The S3067 supports FEC designs with internal divid-
ers or external clocking modes.
Figure 1. System Block Diagram
2.488 Gbps
X
S3076
Clock
Recovery
Unit
2.488
Gbps
X
PERFORMANCE MONITOR
S3067
155 Mbps
Receive
Deserialization
X
S3062
Receive
S3062 167 Mbps S3067 2.67 Gbps
Transmit
FEC Added
X+Y
Transmit
Serialization X + Y
E/O
OPTICAL FIBER
PERFORMANCE MONITOR
O/E
S3076
S3067
S3062
Clock 2.67 Gbps Receive
167 Mbps Receive
Recovery X + Y Deserialization X + Y FEC Data
Unit Stripped Off
S3062
Transmit
155 Mbps
S3067
Transmit
2.488 Gbps
X Serialization X
X = Data
Y = FEC Data
September 17, 2002/ Revision A
1




S3067 pdf, 반도체, 판매, 대치품
S3067
MULTIRATE (OC-48/24/12/3/GBE/FC) SONET/SDH/ATM TRANSCEIVER w/ FEC
Figure 4. S3067 Transceiver Functional Block Diagram
PHINIT
FECSEL[2:0]
RATESEL[0:1]
REFCLKP/N
POCLK (Internal)
RLPTIME
FECSEL2
CAP1
CAP2
TESTEN
3
2
SLPTIME
BYPASS
16
PIN[15:0]
PICLKP/N
BYPASSCLKP/N
CLOCK
SYNTHESIZER
LLEB
N
KILLRXCLK
RSDP/N
D
VCO CLOCK
CLOCKS
TIMGEN
16:1
PARALLEL TXDP/N
TO SERIAL
TXCLKP/N
TIMGEN
TX
LOCKDET
155MCKP/N
19MCK
PCLKP/N
PHERR
D
TSDP/N
TSCLKP/N
RX
POCLKP/N
TXDP/N
(Internal)
RSCLKP/N
TXCLKP/N
(Internal)
DLEB
SQUELCH
SDTTL
SDLVPECL
RSTB
IVREF
D
D
R
1:16
SERIAL TO
PARALLEL
16
POUT[15:0]
OVREF
4 September 17, 2002/ Revision A

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S3067 전자부품, 판매, 대치품
MULTIRATE (OC-48/24/12/3/GBE/FC) SONET/SDH/ATM TRANSCEIVER w/ FEC
S3067
Parallel-to-Serial Converter
The parallel-to-serial converter shown in Figure 4 is
comprised of a FIFO and a parallel-to-serial register.
The FIFO input latches the data from the PIN[15:0]
bus on the rising edge of PICLK. The parallel-to-
serial register is a loadable shift register which takes
its parallel input from the FIFO output.
An internally generated divide-by-16 clock, which is
phase aligned to the transmit serial clock as de-
scribed in the Timing Generator description, activates
the parallel data transfer between registers. The serial
data is shifted out of the parallel-to-serial register at
the TSCLK rate.
FIFO
A FIFO is added to decouple the internal and exter-
nal (PICLK) clocks. The internally generated
divide-by-16 clock is used to clock out data from the
FIFO. PHINIT and LOCKDET are used to center or
reset the FIFO. The PHINIT and LOCKDET signals
will center the FIFO after the third PICLK pulse. This
is to insure that PICLK is stable. This scheme allows
the user to have an infinite PCLK-to-PICLK delay
through the ASIC. Once the FIFO is centered, the
PCLK-to-PICLK delay can have a maximum drift as
specified in Table 20.
FIFO Initialization
The FIFO can be initialized in one of the following
three ways:
1. During power up, once the PLL has locked to
the reference clock provided on the REFCLK
pins, the LOCKDET will go active and initialize
the FIFO.
2. When RSTB goes active, the entire chip is reset.
This causes the PLL to go out of lock and thus
the LOCKDET goes inactive. When the PLL re-
acquires the lock, the LOCKDET goes active
and initializes the FIFO. Note: PCLK is held re-
set when RSTB is active.
3. The user can also initialize the FIFO by raising
PHINIT.
During the normal running operation, the incoming
data is passed from the PICLK timing domain to the
internally generated, divide-by-16 clock timing do-
main. Although the frequency of PICLK and the
internally generated clock is the same, their phase
relationship is arbitrary. To prevent errors caused by
short setup or hold times between the two timing
domains, the timing generator circuitry monitors the
phase relationship between PICLK and the internally
generated clock. When a potential setup or hold time
violation is detected, the phase error goes high.
When PHERR conditions occur, PHINIT should be
activated to recenter the FIFO (at least 2 PCLK peri-
ods). This can be done by connecting PHERR to
PHINIT. When realignment occurs, up to 10 bytes of
data will be lost. The user can also take in the
PHERR signal, process it and send an output to
PHINIT in such a way that idle bytes are lost during
the realignment process. PHERR will go inactive
when the realignment is complete.
Receiver Operation
The S3067 receiver chip provides the first stage of
digital processing of a receive SONET STS-48/STS-
24/STS-12/STS-3/GBE/FC bit-serial stream. The
bit-serial data stream is then converted into a 16-bit
half-word data format. A loopback mode is provided
for diagnostic loopback (transmitter to receiver). A line
loopback (receiver to transmitter) is also provided.
Both line and local loopback modes can be active at
the same time.
Serial-to-Parallel Converter
The serial-to-parallel converter consists of two 16-bit
registers. The first is a serial-in, parallel-out shift reg-
ister, which performs the serial-to-parallel conversion
clocked by the clock recovery block. On the falling
edge of the POCLK, the data in the parallel register
is transferred to an output parallel register which
drives POUT[15:0].
OTHER OPERATING MODES
Diagnostic Loopback
When the Diagnostic Loopback Enable (DLEB) input
is low, a loopback from the transmitter to the re-
ceiver at the serial data rate can be set up for
diagnostic purposes. The differential serial output
data from the transmitter is routed to the serial-to-
parallel block in place of the normal data stream
(RSD). TSD/TSCLK outputs are active. DLEB takes
precedence over SDPECL and SDTTL.
September 17, 2002/ Revision A
7

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