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T15N1024A 데이터시트 PDF




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부품번호 T15N1024A 기능
기능 128K X 8 LOW POWER CMOS STATIC RAM
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T15N1024A 데이터시트, 핀배열, 회로
tm TE
CH
SRAM
T15N1024A
128K X 8 LOW POWER
CMOS STATIC RAM
FEATURES
Low-power consumption
- Active: 40mA at 55ns (Max.)
- CMOS Stand-by: 10uA (Max.)
55/70/100 ns access time
Equal access and cycle time
Single +2.4V to 3.6V Power Supply
TTL compatible , Tri-state output
Common I/O capability
Automatic power-down when deselected
Available in 32-pin SOP ,TSOP-I(8x20mm),
TSOP-I(8x13.4mm) ,48-pin CSP packages
Operating temperature :
Commercial : 0 ~ +70 °C
Industrial : -40 ~ +85 °C
PART NUMBER EXAMPLES
PART NO.
PACKAGE
CODE
Operating
Temperature
T15N1024A-55D D=SOP
T15N1024A-70H
T15N1024A-100P
H=TSOP-I(8x20)
P=TSOP-I(8x13.4)
0 ~ +70 °C
T15N1024A-100C C=CSP
T15N1024A-55DI D=SOP
T15N1024A-70HI H=TSOP-I(8x20)
T15N1024A-100PI P=TSOP-I(8x13.4)
-40 ~ +85 °C
T15N1024A-100CI C=CSP
GENERAL DESCRIPTION
The T15N1024A is a very Low Power CMOS
Static RAM organized as 131,072 words by 8 bits.
That operates on a wide voltage range from 2.4V
to 3.6V power supply, Fabricated using high
performance CMOS technology, Inputs and
three-state outputs are TTL compatible and allow
for direct interfacing with common system bus
structures. Data retention is guaranteed at a power
supply voltage as low as 1.5V.
BLOCK DIAGRAM
Vcc
Vss
A0 DECODER
.
.
.
A16
CORE
ARRAY
WE
OE CONTROL
CE1 CIRCUIT
CE2
DATA I/O
I/O1
..
I/O8
TM Technology Inc. reserves the right
P. 1
to change products or specifications without notice.
Publication Date: FEB. 2003
Revision:E




T15N1024A pdf, 반도체, 판매, 대치품
tm TE
CH
T15N1024A
OPERATING CHARACTERISTICS
(Vcc = 2.4 to 3.6V, Gnd = 0V, Ta = 0 ~ +70 °C /-40°C to 85°C)
PARAMETER SYM. TEST CONDITIONS
Input Leakage
Current
ILI
Vcc = Max,
VIN = Gnd to Vcc
CE1 = VIH or CE2= VIL
Output Leakage
Current
ILOor OE = VIH
or WE = VIL
VOUT= Gnd to Vcc
CE1 = VIL,CE2= VIH,
Operating Power
Supply Current
ICC
WE =VIH, OE = VIH ,
VIN = VIH or VIL,
IOUT=0mA
Cycle time=1us,
100% duty, IOUT=0mA,
ICC1 CE1 0.2V,
Average Operating
Current
CE2 VCC-0.2V,
VIN 0.2V
Cycle time=min,
ICC2
100% duty, IOUT=0mA,
CE1 = VIL,CE2= VIH ,
VIN = VIH or VIL
Standby Power
Supply Current
(TTL Level)
CE1 =VIH
ISB CE2= VIL
CE1 Vcc-0.2V,
Standby Power
Supply Current
(CMOS Level)
ISB1
Output Low Voltage VOL
Output High Voltage VOH
CE2 VCC-0.2V
or CE2 0.2V
VIN 0.2V or
VIN Vcc-0.2V
IOL = 1.0mA
IOH = -0.5 mA
-55
Min Max
-1
-1
-2
-3
- 40
- 0.5
- 10
- 0.4
2.1 -
-70
Min Max
-1
-1
-2
-3
- 35
- 0.5
- 10
- 0.4
2.1 -
-100
Min Max
-1
-1
-2
-3
- 25
- 0.5
- 10
- 0.4
2.1 -
UNIT
uA
uA
mA
mA
mA
mA
uA
V
V
TM Technology Inc. reserves the right
P. 4
to change products or specifications without notice.
Publication Date: FEB. 2003
Revision:E

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T15N1024A 전자부품, 판매, 대치품
tm TE
CH
TIMING WAVEFORMS
READ CYCLE 1
(Address Controlled)
Address
tAA
tOH
Dout Previous Data Vaild
tRC
Data Vaild
READ CYCLE 2
(Chip Enable Controlled)
CE1
T15N1024A
DON'T CARE
UNDEFINED
CE2
Dout
tACE
tLZ
tHZ
DON'T CARE
UNDEFINED
Notes (READ CYCLE) :
1. WE are high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition referenced to
VOH or VOL levels.
4. At any given temperature and voltage condition. tHZ (max.) is less than tLZ (min.) both for a given device
and from device to device interconnection.
5. Transition is measured ±200mV from steady state voltage with load. This parameter is sampled and not
100% tested.
6. Device is continuously selected with CE1 =VIL .
TM Technology Inc. reserves the right
P. 7
to change products or specifications without notice.
Publication Date: FEB. 2003
Revision:E

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T15N1024A

128K X 8 LOW POWER CMOS STATIC RAM

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