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PDF AN214 Data sheet ( Hoja de datos )
| Número de pieza | AN214 | |
| Descripción | 74F Extended Octal-Plus Family Applications | |
| Fabricantes | Philips | |
| Logotipo |  |
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INTEGRATED CIRCUITS
AN214
74F extended octal-plus family applications
June 1988
(Revised June 1996)
Philips
Semiconductors
1 page  
Philips Semiconductors
74F extended octal-plus family applications
Application note
AN214
F821/2
F841/2
OE
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
GND
F823/4
F843/4
OE
D0
D1
D2
D3
D4
D5
D6
D7
D8
MR
GND
F825/6
F845/6
OE0
OE1
D0
D1
D2
D3
D4
D5
D6
D7
MR
GND
1
2
3
4
5
6
7
8
9
10
11
12
DQ
CR
DQ
CR
DQ
CR
DQ
CR
DQ
CR
DQ
CR
DQ
CR
DQ
CR
F825/6 F823/4 F821/2
F845/6 F843/4 F841/2
24 VCC
VCC
VCC
23
OE2
O0/O0
O0/O0
22 O0/O0 O1/O1 O1/O1
21 O1/O1 O2/O2 O2/O2
20 O2/O2 O3/O3 O3/O3
19 O3/O3 O4/O4 O4/O4
18 O4/O4 O5/O5 O5/O(5
17 O5/O5 O6/O6 O6/O6
16 O6/O6 O7/O7 O7/O7
15 O7/O7 O8/O8 O8/O8
14 EN
EN O9/O9
13
CP/LE
CP/LE
CP/LE
CP→821–6
LE→841–6
Figure 4. 74F82X and 74F84X Registered/Latched Buffer Pin Configurations
SF01332
F827/8
Buffers
10-bit
OE0
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
GND
F861/2
Xcvrs
10-bit
OEBA
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
GND
F863/4
Xcvrs
9-bit
OEBA0
A0
A1
A2
A3
A4
A5
A6
A7
A8
OEBA1
GND
1
2
3
4
5
6
7
8
9
10
11
12
F863/4
Xcvrs
9-bit
F861/2
Xcvrs
10-bit
F827/8
Buffers
10-bit
24 VCC
VCC
VCC
23 B0/B0
B0/B0
O0/O0
22 B1/B1
B1/B1
O1/O1
21 B2/B2
B2/B2
O2/O2
20 B3/B3
B3/B3
O3/O3
19 B4/B4
B4/B4
O4/O4
18 B5/B5
B5/B5
O5/O(5
17 B6/B6
B6/B6
O6/O6
16 B7/B7
B7/B7
O7/O7
15 B8/B8
B8/B8
O8/O8
14 OEAB0
B9/B9
O9/O9
13 OEAB1 CP/LE
CP/LE
June 1988
Figure 5. 74F827/8 and 74F861–4 Buffers and Transceivers Pin Configurations
5
SF01333
5 Page 
Philips Semiconductors
74F extended octal-plus family applications
Application note
AN214
Metastability in Latches and Registers
Interfacing a basically asynchronous real-world with synchronous
logic systems can and does cause many circuit designer
headaches. The problem: latches and registers which are normally
considered to have only two stable states (High and Low) actually
have a third—The METASTABLE State. This third operating point
occurs when the corss-coupled latch is exactly balanced. This state
is only stable when there is no noise on the chip which would tend to
destabilize the perfect energy balance between the bi-stable states
of the latch. Refer to Figure 12.
Metastability can occur when input data violate the setup time or
hold time specifications at the clocking or strobing edge of the
synchronizing clock input. With no system noise, the latch cannot
decide “yes or no”, so it is possible for the latch to “go metastable”
or “maybe”. With noise on the chip, random energy will “nudge” the
latch toward one of its “bi-stable” states—HIGH or LOW. This
metastable state time can range from nanoseconds to milliseconds.
With today’s very high performance logic families, the metastable
condition can last for, perhaps, 1000 times the latch’s normal
propagation delay time. A metastable latch has an unpredictable
delay time during which the output is between logic levels. This
metastable state can easily last more than 50ns with today’s high
performance logic families and WILL cause systems to “crash” if
great care is not taken with asynchronous, real-world interfacing.
The D-type latch shown in Figure 12 has DATA applied to NAND
gate 1 and DATA applied to NAND gate 2. When the LE (Latch
Enable) input is LOW, gates 1 and 2 outputs are HIGH and the G3/4
R-S latch is latched and stable. When LE is HIGH, the latch appears
to be transparent to the DATA input—Q equals DATA. On the
HIGH-to-LOW transition of LE, the DATA logic level that meets the
latch’s setup and hold time is stored in the latch.
If DATA changes during the setup time to hold time period, it is
possible for both outputs of gates 1 and 2 to be in the input
thresholds region of gates 3 and 4, respectively. Under these
conditions, the latch (gates 3 and 4) could be perfectly balanced in
the METASTABLE state. Eventually, chip and system noise will
cause the latch to be forced into a HIGH/LOW stable state.
The Extended Octal-Puls Family, while not entirely immune, has
been made metastable resistant by using design techniques which
force the latch toward a stable state much more quickly than older
bus interface families.
DATA
G1
G3 Q
5.0
G2
LE
G4 Q
4.0
3.0
METASTABLE POINT
VOUT — OUTPUT VOLTAGE
↑
ENERGY
VOG3 = VIG4
↓
VTH = 1.35V
↑
ENERGY
2.0
1.0
VOG3 = VIG4
↓
VTH = 1.35V
LOW
HIGH
0
0
0.5 1.0 1.5
2.0 2.5
VIN — INPUT VOLTAGE
SF01339
Figure 12. Metastability in Latches and Registers
June 1988
11
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet AN214.PDF ] | |
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