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PDF LT1310 Data sheet ( Hoja de datos )
| Número de pieza | LT1310 | |
| Descripción | 1.5A Boost DC/DC Converter with Phase-Locked Loop | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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LT1310
1.5A Boost
DC/DC Converter
with Phase-Locked Loop
FEATURES
s Synchronizable or Constant Frequency
Low Noise Output
s Synchronizable Up to 4.5MHz
s Wide Input Voltage Range: 2.8V to 18V
s Low Profile Surface Mount Solution
(All Ceramic Capacitors)
s Low VCESAT Switch: 240mV at 1A
s Adjustable Output from VIN to 35V
s Small Thermally Enhanced 10-Lead MSOP Package
U
APPLICATIO S
s Instruments
s Avionics
s Data Acquisition
s Communications
s Imaging
s Ultrasound
DESCRIPTIO
The LT®1310 boost DC/DC converter combines a 1.5A
current mode PWM switcher with an integrated phase-
locked loop, allowing the user to set the switching fre-
quency anywhere from 10kHz to 4.5MHz. Intended for use
in applications where switching frequency must be accu-
rately controlled, the LT1310 can generate 12V at up to
400mA from a 5V input.
Switching frequency is set with an external capacitor, and
the device can be operated in either free-running or phase-
locked mode. A wide capture range of nearly 2:1 allows the
free-running frequency to be set using standard ±10%
tolerance NP0 dielectric capacitors.
The LT1310 is available in the tiny thermally enhanced
10-lead MSOP package.
, LTC and LT are registered trademarks of Linear Technology Corporation.
TYPICAL APPLICATIO
VIN
5V
SHUTDOWN
SYNC
1.6MHz
L1
5.6µH
D1
C1
4.7µF
CERAMIC
3.01k
1500pF
LT1310
VIN
SHDN
SW
FB
SYNC
PLL-LPF
VC
CT
GND*
15k
820pF
100pF
NP0
C1: 4.7µF, X5R OR X7R, 6.3V
C2: 4.7µF, X5R OR X7R, 16V
D1: MICROSEMI UPS120 OR EQUIVALENT
L1: PANASONIC ELL6SH-5R6M
*EXPOSED PAD MUST ALSO BE GROUNDED
178k
VOUT
12V
400mA
20.5k
C2
4.7µF
CERAMIC
1310 F01a
Figure 1. 5V to 12V Converter Synchronized at 1.6MHz
LT1310 Efficiency
90
VOUT = 12V
85
80 3.3VIN
75
5VIN
70
65
60
55
50
45
40
35
0
100 200 300
LOAD CURRENT (mA)
400
1310 F01b
1310f
1
1 page  
LT1310
PI FU CTIO S
FB (Pin 1): Feedback Pin for Error Amplifier. Connect the
resistor divider here to set output voltage according to
the formula:
VOUT = 1.255(1 + R1/R2)
VOUT
R1
FB
R2
Minimize trace area at this pin.
SHDN (Pin 2): Shutdown Pin. For active mode, tie this pin
to a voltage between 2.4V and 18V. To disable the part and
go into low current mode, pull this pin below 0.4V.
PLL-LPF (Pin 3): Phase Locked-Loop Filter Pin. This is the
output of the phase detector and also the input to the
voltage controlled oscillator (VCO). Connect an RC filter
here. Typically, R = 3k and C = 1500pF. The voltage range
at the PLL-LPF pin is approximately 0V to 1.5V with 1.5V
corresponding to the maximum switching frequency. For
applications not requiring synchronization, use a pull-up
resistor at this pin; the pull-up voltage must be above 2.4V.
Set the pull-up resistor value according to:
( )RPULLUP =
VPULLUP – 1.5V
300µA
For a pull-up voltage of 5V:
RPULLUP
=
(5V – 1.5V)
300µA
≈
11.6k
SYNC (Pin 4): Frequency Synchronization Pin. Inject the
external synchronizing signal here. The phase detector is
edge triggered and when locked the rising edge of the
sync signal will be aligned with the turn-on of the power
transistor. The SYNC signal must have a minimum HIGH
amplitude of 1.2V and a maximum LOW amplitude of
0.2V with the signal staying low for at least 100ns.
1.2V (MIN)
0.2V (MAX)
100ns (MIN)
GND (Pin 5, Exposed Pad): Ground. Tie both Pin 5 and
the exposed pad directly to local ground plane. The
ground metal to the exposed pad should be wide for better
heat dissipation. Multiple vias (local ground plane ↔
ground backplane) placed close to the exposed pad can
further aid in reducing thermal resistance. The exposed
pad must be soldered to ground for the LT1310 to function
properly.
SW (Pins 6, 7): Switch Pin. Connect inductor/diode here.
Minimize trace area at this pin to keep EMI down.
VIN (Pin 8): Supply Pin. Must be bypassed as close as
possible to the pin.
CT (Pin 9): Timing Capacitor Pin for VCO. Place the timing
capacitor from this pin to ground to set the frequency
range for the oscillator. Minimize trace at this pin to reduce
stray capacitance.
VC (Pin 10): Compensation Pin for Error Amplifier. Tie an
RC network here to compensate the voltage feedback
loop.
1310f
5
5 Page 
LT1310
APPLICATIO S I FOR ATIO
Layout Hints
The high speed operation of the LT1310 demands careful
attention to board layout. You will not get advertised
performance with careless layout. Figure 6 shows the
recommended component placement for a boost
converter.
CC RC
R1 R2 CT
VIN
CIN
SHDN
LT1310
L1
SYNC
RLP
CLP
COUT
SW
MULTIPLE VIAS
D1
GND
VOUT
1310 F06
Figure 6. Recommended Component Placement for Boost Converter. Note Direct High Current Paths Using Wide PC Traces. Minimize
Trace Area at Pin 10 (VC), Pin 9 (CT) and Pin 1 (FB). Use Multiple Vias to Tie Pin 5 Copper and the Exposed Pad to Ground Plane. Use
Vias at One Location Only to Avoid Introducing Switching Currents Into the Ground Plane
PACKAGE DESCRIPTIO
MSE Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1663)
0.254
(.010)
GAUGE PLANE
DETAIL “A”
0° – 6° TYP
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
10 9 8 7 6
0.497 ± 0.076
(.0196 ± .003)
REF
4.90 ± 0.15
(1.93 ± .006)
3.00 ± 0.102
(.118 ± .004)
NOTE 4
12345
BOTTOM VIEW OF
EXPOSED PAD OPTION
2.06 ± 0.102
1 (.081 ± .004)
1.83 ± 0.102
(.072 ± .004)
10
0.53 ± 0.01
(.021 ± .006)
DETAIL “A”
1.10
(.043)
MAX
0.18
(.007)
SEATING
PLANE 0.17 – 0.27
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
(.007 – .011)
TYP
0.50
(.0197)
BSC
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.86
(.034)
REF
2.794 ± 0.102
(.110 ± .004)
0.889 ± 0.127
(.035 ± .005)
0.13 ± 0.076
(.005 ± .003)
5.23
(.206)
MIN
2.083 ± 0.102 3.2 – 3.45
(.082 ± .004) (.126 – .136)
MSOP (MSE) 0802
0.305 ± 0.038
(.0120 ± .0015)
TYP
0.50
(.0197)
BSC
RECOMMENDED SOLDER PAD LAYOUT
1310f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet LT1310.PDF ] | |
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