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부품번호 MTV030 기능
기능 On-Screen Display with Auto-Sizing Controller
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MTV030 데이터시트, 핀배열, 회로
MYSON
TECHNOLOGY
MTV030
On-Screen Display with Auto-Sizing Controller
FEATURES
• Horizontal SYNC input up to 150 KHz.
• On-chip PLL circuitry up to 150 MHz.
• Minimum timing measurement among HFLB, VFLB, RIN,
GIN and BIN for auto sizing.
• Full screen self-test pattern generator.
• Programmable Hor. resolutions up to 1524 dots per line.
• Full-screen display consists of 15 (rows) by 30 (columns)
• Two font size 12x16 or 12x18 dot matrix per character.
• True totally 512 mask ROM fonts including 496 standard
fonts and 16 multi-color fonts.
• Double character height and/or width control.
• Programmable positioning for display screen center.
• Character bordering, shadowing and blinking effect.
• Programmable character height (18 to 71 lines) control.
• Row to row spacing control to avoid expansion distortion.
• 4 programmable windows with multi-level operation.
• Shadowing on windows with programmable shadow
width/height/color.
• Programmable adaptive approach to handle H, V sync
collision automatically by hardware.
• Software clears bit for full-screen erasing.
• Fade-in/fade-out or blending-in/blending-out effects.
• 5-channel/8-bit PWM D/A converter output.
• Compatible with SPI bus or I2C interface with slave
address 7AH/7BH (slave address is mask option).
• 16-pin, 20-pin or 24-pin PDIP package.
GENERAL DESCRIPTION
MTV030 is designed for monitor applications to display
built-in characters or fonts onto monitor screens. The dis-
play operation occurs by transferring data and control infor-
mation from the micro-controller to RAM through a serial
data interface. It can execute full-screen display automati-
cally, as well as specific functions such as character back-
ground, bordering, shadowing, blinking, double height and
width, font by font color control, frame positioning, frame
size control by character height and row-to-row spacing,
horizontal display resolution, full-screen erasing, fade-in/
fade-out effect, windowing effect, shadowing on window
and full-screen self-test pattern generator.
MTV030 provides true 512 fonts including 496 standard
fonts and 16 multi-color fonts and 2 font sizes, 12x16 or
12x18 for more efficacious applications. So each one of the
512 fonts can be displayed at the same time. The full OSD
menu is formed by 15 rows x 30 columns, which can be
positioned anywhere on the monitor screen by changing
vertical or horizontal delay.
The auto sizing video measurement module measure
the timing relationship among HFLB, VFLB, and R, G, BIN
at the speed related to the OSD resolution. MCU can get
the measurement data, active video, front porth and back
porth, through I2C bus read/write operation to keep the
appropriate display size and center.
BLOCK DIAGRAM
SSB
SCK
SDA
VFLB
HFLB
RP
VCO
PWM0
PWM1
PWM2
PWM3
PWM4
SERIAL DATA
INTERFACE
8DATA
9ROW, COL
ACK
ARWDB
HDREN
VDREN
NROW
ADDRESS BUS
ADMINISTRATOR
5 RCADDR
9 DADDR
9 FONTADDR
5 WINADDR
5 PWMADDR
VSP
CH 7
CHS
VERTD 8
VERTICAL
DISPLAY
CONTROL
5 LPN
NROW
VDREN
HORIZONTAL
ARWDB
HSP HORD 8 DISPLAY CONTROL HDREN
PHASE LOCK LOOP VCLKX
PWM D/A
CONVERTER
8 DATA
POWER ON RESET PRB
DATA 8
CWS
CHS
DISPLAY & ROW
CONTROL
REGISTERS
LUMAR
LUMAG
LUMAB
BLINK
8 CRADDR
DATA 8
LPN 5
CWS
VCLKS
CHARACTER ROM
LUMINANCE &
BORDGER
GENERATOR
LUMA
BORDER
DATA 8
8 VERTD
8 HORD
7 CH
WINDOWS &
FRAME
CONTROL
BSEN
SHADOW
OSDENB
HSP
VSP
LUMAR
LUMAG
LUMAB
BLINK
VCLKX
COLOUR
ENCODER
DATA 8 AUTO SIZING
MEASUREMENT
VDD
VSS
VDDA
VSSA
ROUT
GOUT
BOUT
FBKG
HTONE
RIN
GIN
BIN
This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification without notice.
No liability is assumed as a result of the use of this product. No rights under any patent accompany the sales of the product.
1/21 MTV030 Revision 1.0 10/15/1999




MTV030 pdf, 반도체, 판매, 대치품
MYSON
TECHNOLOGY
MTV030
3.0 FUNCTIONAL DESCRIPTIONS
3.1 SERIAL DATA INTERFACE
The serial data interface receives data transmitted from an external controller. And there are 2 types of bus
can be accessed through the serial data interface, one is SPI bus and other is I2C bus.
3.1.1 SPI bus
While SSB pin is pulled to "high" or "low" level, the SPI bus operation is selected. And a valid transmission
should be starting from pulling SSB to "low" level, enabling MTV030 to receiving mode, and retain "low" level
until the last cycle for a complete data packet transfer. The protocol is shown in Figure 1.
SSB
SCK
SDA
MSB
LSB
first byte
last byte
FIGURE 1. Data Transmission Protocol (SPI)
There are three transmission formats shown as below:
Format (a) R - C - D R - C - D R - C - D .....
Format (b) R - C - D C - D C - D C - D .....
Format (c) R - C - D D D D D D .....
Where R=Row address, C=Column address, D=Display data
3.1.2 I2C bus
I2C bus operation is only selected when SSB pin is left floating. And a valid transmission should be starting
from writing the slave address 7AH(write mode), or 7BH(read mode) to MTV030. The protocol is shown in
Figure 2. And the auto sizing video measurement data (total 10 bytes) are read only registers and the others
are write only registers.
SCK
SDA
START
B7 B6 B0 B7
B0
first byte
ACK
second byte
last byte
FIGURE 2. Data Transmission Protocol (I2C)
ACK
STOP
There are three transmission formats for I2C write mode shown as below:
Format (a) S - R - C - D R - C - D R - C - D .....
Format (b) S - R - C - D C - D C - D C - D .....
Format (c) S - R - C - D D D D D D .....
Where S=Slave address, R=Row address, C=Column address, D=Display data
And there is one transmission format for I2C read mode shown as below:
Format (a) S D D D D D D D D D D dummy D dummy D .....
Where S=Slave address, D=Measurement data
4/21 MTV030 Revision 1.0 10/15/1999

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MTV030 전자부품, 판매, 대치품
MYSON
TECHNOLOGY
MTV030
3.4 Horizontal display control
The horizontal display control is used to generate control timing for horizontal display based on double char-
acter width bit (CWS), horizontal positioning register (HORD), horizontal resolution register (HORR), and
HFLB input. A horizontal display line consists of (HORR*12) dots which include 360 dots for 30 display char-
acters and the remaining dots for blank region. The horizontal delay starting from HFLB leading edge is calcu-
lated with the following equation,
Horizontal delay time = ( HORD * 6 + 49) * P - phase error detection pulse width
Where P = One pixel display time = One horizontal line display time / (HORR*12)
3.5 Phase lock loop (PLL)
On-chip PLL generates system clock timing (VCLK) by tracking the input HFLB and horizontal resolution reg-
ister (HORR). The frequency of VCLK is determined by the following equation:
VCLK Freq = HFLB Freq * HORR * 12
The VCLK frequency ranges from 6MHz to 150MHz selected by (VCO1, VCO0). In addition, when HFLB input
is not present to MTV030, the PLL will generate a specific system clock, approximately 2.5MHz, by a built-in
oscillator to ensure data integrity.
3.6 Display & Row control registers
The internal RAM contains display and row control registers. The display registers have 450 locations which
are allocated between (row 0, column 0) to (row 14, column 29), as shown in Figure 4 and Figure 5. Each dis-
play register has its corresponding character address on ADDRESS byte, its corresponding background color,
1 blink bit and its corresponding color bits on ATTRIBUTE bytes. The row control register is allocated at col-
umn 30 for row 0 to row 14 of attribute bytes, it is used to set character size to each respective row. If double
width character is chosen, only even column characters could be displayed on screen and the odd column
characters will be hidden.
ROW #
01
0
1
13
14
COLUMN #
CHARACTER ADDRESS BYTES
of DISPLAY REGISTERS
28 29
30
ROW
ATTRIBUTE
CRTL REG
31
R
E
S
E
R
V
E
D
FIGURE 4. Address Bytes of Display Registers Memory Map
7/21 MTV030 Revision 1.0 10/15/1999

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