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PDF MTV021 Data sheet ( Hoja de datos )

Número de pieza MTV021
Descripción Enhanced Super On-Screen Display
Fabricantes Myson 
Logotipo Myson Logotipo



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No Preview Available ! MTV021 Hoja de datos, Descripción, Manual

MYSON
TECHNOLOGY
MTV021
Enhanced Super On-Screen Display
FEATURES
• Horizontal SYNC input up to 130 KHz.
• On-chip PLL circuitry up to 96 MHz.
• Programmable horizontal resolutions up to 1524 dots per
display row.
• Full-screen display consists of 15 (rows) by 30 (columns)
characters.
• 12 x 18 dot matrices per character.
• Total of 272 characters and graphic fonts, including 256
standard and 16 multi-color mask ROM fonts.
• 8 color-selectable maximum per display character.
• 7 color-selectable maximum for character background.
• Double character height and/or width control.
• Programmable positioning for display screen center.
• Bordering, shadowing and blinking effect.
• Programmable character height (18 to 71 lines) control.
• Row to row spacing register to manipulate the constant
display height.
• 4 programmable background windows with multi-level
operation and shadowing on window effect.
• Software clears bit for full-screen erasing.
• Half tone and fast blanking output.
• Fade-in/fade-out effect.
• 8-channel/8-bit PWM D/A converter output.
• Compatible with SPI bus or I2C interface with slave
address 7AH (slave address is mask option).
• 16-pin, 20-pin or 24-pin PDIP package.
GENERAL DESCRIPTION
MTV021 is designed for monitor applications to
display built-in characters or fonts onto monitor
screens. The display operation occurs by transferring
data and control information from the micro-controller
to RAM through a serial data interface. It can execute
full-screen display automatically, as well as specific
functions such as character background color, bor-
dering, shadowing, blinking, double height and width,
font by font color control, frame positioning, frame
size control by character height and row-to-row spac-
ing, horizontal display resolution, full-screen erasing,
fade-in/fade-out effect, windowing effect and shad-
owing on window.
MTV021 provides 256 standard and 16 multi-color
characters and graphic fonts for more efficacious
applications. The full OSD menu is formed by 15
rows x 30 columns, which can be positioned any-
where on the monitor screen by changing vertical or
horizontal delay.
Moreover, MTV021 also provides 8 PWM DAC
channels with 8-bit resolution and a PWM clock out-
put for external digital-to-analog control.
BLOCK DIAGRAM
SSB
SCK
SDA
VFLB
HFLB
RP
VCO
PWM0
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
PWM7
SERIAL DATA
INTERFACE
8DATA
9ROW, COL
ACK
ARWDB
HDREN
VDREN
NROW
ADDRESS BUS
ADMINISTRATOR
5 RCADDR
9 DADDR
9 FONTADDR
5 WINADDR
5 PWMADDR
VSP
CH 7
CHS
VERTD 8
VERTICAL
DISPLAY
CONTROL
5 LPN
NROW
VDREN
HORIZONTAL
ARWDB
HSP HORD 8 DISPLAY CONTROL HDREN
PHASE LOCK LOOP VCLKX
PWM D/A
CONVERTER
8 DATA
DATA 8
CWS
CHS
DISPLAY & ROW
CONTROL
REGISTERS
LUMAR
LUMAG
LUMAB
BLINK
8 CRADDR
DATA 8
LPN 5
CWS
VCLKS
CHARACTER ROM
LUMINANCE &
BORDGER
GENERATOR
LUMA
BORDER
DATA8
8 VERTD
8 HORD
7 CH
WINDOWS &
FRAME
CONTROL
BSEN
SHADOW
OSDENB
HSP
VSP
LUMAR
LUMAG
LUMAB
BLINK
VCLKX
COLOUR
ENCODER
POWER ON
RESET
PRB
VDD
VSS
VDDA
VSSA
ROUT
GOUT
BOUT
FBKG
HTONE
This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification without notice.
No liability is assumed as a result of the use of this product. No rights under any patent accompany the sales of the product.
1/17
MTV021 Revision 5.0 6/29/1999

1 page




MTV021 pdf
MYSON
TECHNOLOGY
MTV021
The data transmission is permitted to change from format (a) to format (b) and (c), or from format (b) to format
(a), but not from format (c) back to format (a) and (b). The alternation between transmission formats is config-
ured as the state diagram shown in Figure 3.
0, X
Initiate
Input = b7, b6
1, X
format (a)
1, X ROW
format (c) 0, 1
COL
c
0, 1
format (b)
0, 0
COL
ab
1, X
X, X DA
c
DA
ab
FIGURE 3. Transmission State Diagram
3.2 Address bus administrator
The administrator manages bus address arbitration of internal registers or user fonts RAM during external
data write in. The external data write through serial data interface to registers must be synchronized by inter-
nal display timing. In addition, the administrator also provides automatic increment to address bus when exter-
nal write using format (c).
3.3 Vertical display control
The vertical display control can generates different vertical display sizes for most display standards in current
monitors. The vertical display size is calculated with the information of double character height bit(CHS), verti-
cal display height control register(CH6-CH0).The algorithm of repeating character line display are shown as
Table 2 and Table 3. The programmable vertical size range is 270 lines to maximum 2130 lines.
The vertical display center for full screen display could be figured out according to the information of vertical
starting position register (VERTD) and VFLB input. The vertical delay starting from the leading edge of VFLB,
is calculated with the following equation:
Vertical delay time = ( VERTD * 4 + 1 ) * H
Where H = one horizontal line display time
TABLE 2. Repeat line weight of character
CH6 - CH0
CH6,CH5=11
CH6,CH5=10
CH6,CH5=0x
CH4=1
Repeat Line Weight
+18*3
+18*2
+18
+16
5/17
MTV021 Revision 5.0 6/29/1999

5 Page





MTV021 arduino
MYSON
TECHNOLOGY
MTV021
PWMCK - Select the output options to HTONE/PWMCK pin.
= 0 HTONE option is selected.
= 1 PWMCK option is selected with 50/50 duty cycle and synchronous with the input HFLB.
The frequency is selected by (VCO1, VCO0) shown as Table 5.
The initial value is 0 after power up.
SELVCL - Enable auto detection for horizontal and vertical syncs input edge distorition to avoid unstable
Vsync leading mismatch with Hsync signal while the bit is set to "1". The initial value is 0 after
power up.
HSP -
= 1 Accept positive polarity Hsync input.
= 0 Accept negative polarity Hsync input.
VSP -
= 1 Accept positive polarity Vsync input.
= 0 Accept negative polarity Vsync input.
VCO1, VCO0 - Select the appropriate curve partitions of VCO frequency to voltage based on HFLB input and
horizontal resolution register (HORR). And there are different curve partitions based on differ-
ent application resister value on pin 3 (pin RP) as belows:
(i) 12K ohm:
= (0, 0) 6MHz < Pixel rate < 12MHz
= (0, 1) 12MHz < Pixel rate < 24MHz
= (1, 0) 24MHz < Pixel rate < 48MHz
= (1, 1) 48MHz < Pixel rate < 96MHz
(ii) 11K ohm:
= (0, 0) 6.5MHz < Pixel rate < 13MHz
= (0, 1) 13MHz < Pixel rate < 26MHz
= (1, 0) 26MHz < Pixel rate < 52MHz
= (1, 1) 52MHz < Pixel rate < 96MHz
(iii)10K ohm:
= (0, 0) 7MHz < Pixel rate < 14MHz
= (0, 1) 14MHz < Pixel rate < 28MHz
= (1, 0) 28MHz < Pixel rate < 56MHz
= (1, 1) 56MHz < Pixel rate < 96MHz
(iv)9.1K ohm:
= (0, 0) 7.5MHz < Pixel rate < 15MHz
= (0, 1) 15MHz < Pixel rate < 30MHz
= (1, 0) 30MHz < Pixel rate < 60MHz
= (1, 1) 60MHz < Pixel rate < 96MHz
(v)8.2K ohm:
= (0, 0) 8MHz < Pixel rate < 16MHz
= (0, 1) 16MHz < Pixel rate < 32MHz
= (1, 0) 32MHz < Pixel rate < 64MHz
= (1, 1) 64MHz < Pixel rate < 96MHz
(vi)7.5K ohm:
= (0, 0) 8.5MHz < Pixel rate < 17MHz
= (0, 1) 17MHz < Pixel rate < 34MHz
= (1, 0) 34MHz < Pixel rate < 68MHz
= (1, 1) 68MHz < Pixel rate < 96MHz
(vii)under or equal to 6.2K ohm:
= (0, 0) 9.5MHz < Pixel rate < 19MHz
= (0, 1) 19MHz < Pixel rate < 38MHz
= (1, 0) 38MHz < Pixel rate < 76MHz
11/17
MTV021 Revision 5.0 6/29/1999

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