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MTV012E 데이터시트 PDF




Myson에서 제조한 전자 부품 MTV012E은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


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부품번호 MTV012E 기능
기능 8051 Embedded CRT Monitor Controller OTP Version
제조업체 Myson
로고 Myson 로고


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MTV012E 데이터시트, 핀배열, 회로
MYSON
TECHNOLOGY
MTV012E
8051 Embedded CRT Monitor Controller
OTP Version
FEATURES
8051 core.
256 bytes internal RAM.
8K bytes program EPROM.
14 channels 12V open drain PWM DAC, 10 dedicated channels and 4 channels shared with I/O pin.
20 bi-direction I/O pin, 12 dedicated pin, 4 shared with DAC, 4 shared with DDC/IIC interface.
3 output pin shared with H/V sync output and self test output pins.
SYNC processor for composite separation, polarity and frequency check, and polarity adjust.
Built-in monitor self test pattern generator.
Built-in Low Power Reset circuit.
IIC interface for DDC1/DDC2B and EEPROM, only one EEPROM needed to store DDC1/DDC2B and
display mode information.
Watch dog timer with programmable interval.
40 pin PDIP package.
GENERAL DESCRIPTION
The MTV012E micro-controller is an 8051 CPU core-embedded device specially tailored to CRT monitor
applications. It includes an 8051 CPU core, 256-byte SRAM, 14 built-in PWM DACs, DDC1/DDC2B
interface, 24Cxx series EEPROM interface and an 8K-byte internal program EPROM.
BLOCK DIAGRAM
P1.0-7
P0.0-7
RD
X1 WR
8051
X2 CORE INT1
P2.0-3
RST
P3.0-P3.2 P3.4 P2.4-7
P0.0-7
RD
WR
XFR
WATCH-DOG
TIMER
RST
STOUT
HSYNC
H/VSYNC VSYNC
CONTROL HBLANK
VBLANK
14 CHANNEL DA0-9
PWM DAC
DA10-13
HSCL
HSDA
DDC 1/2 B & FIFO
INTERFACE
ISCL
IIC INTERFACE
ISDA
This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification
without notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the
product.
1/14
MTV012E Revision 1.2 12/23/1998




MTV012E pdf, 반도체, 판매, 대치품
MYSON
TECHNOLOGY
MTV012E
DA11E = 1 Pin #27 is DA11.
= 0 Pin #27 is P2.6.
DA10E = 1 Pin #28 is DA10.
= 0 Pin #28 is P2.7.
* SINT0 should be 0 in this case.
2. External Special Function Registers (XFR)
The XFR is a group of registers allocated in the 8051 external RAM area. Most of the registers are used
for monitor control or PWM DAC. The program can initialize Ri value and use "MOVX" instruction to
access these registers.
3. PWM DAC
Each D/A converter's output pulse width is controlled by an 8-bit register in the XFR. The frequency of
these outputs is (Xtal frequency)/253 or (Xtal frequency)/256, selected by DIV253. If DIV253=1, writing
FDH/FEH/FFH to the DAC register generates a stable high output. If DIV253=0, the output will pulse low
at least once even if the DAC register's content is FFH. Writing 00H to the DAC register generates stable
low output.
reg name
DA0
DA1
DA2
DA3
DA4
DA5
DA6
DA7
DA8
DA9
DA10
DA11
DA12
DA13
WDT
addr
20h (r/w)
21h (r/w)
22h (r/w)
23h (r/w)
24h (r/w)
25h (r/w)
26h (r/w)
27h (r/w)
28h (r/w)
29h (r/w)
2Ah (r/w)
2Bh (r/w)
2Ch (r/w)
2Dh (r/w)
80h
bit7
DA0b7
DA1b7
DA2b7
DA3b7
DA4b7
DA5b7
DA6b7
DA7b7
DA8b7
DA9b7
DA10b7
DA11b7
DA12b7
DA13b7
WEN
bit6
DA0b6
DA1b6
DA2b6
DA3b6
DA4b6
DA5b6
DA6b6
DA7b6
DA8b6
DA9b6
DA10b6
DA11b6
DA12b6
DA13b6
WCLR
bit5
DA0b5
DA1b5
DA2b5
DA3b5
DA4b5
DA5b5
DA6b5
DA7b5
DA8b5
DA9b5
DA10b5
DA11b5
DA12b5
DA13b5
CLRDDC
bit4
DA0b4
DA1b4
DA2b4
DA3b4
DA4b4
DA5b4
DA6b4
DA7b4
DA8b4
DA9b4
DA10b4
DA11b4
DA12b4
DA13b4
DIV253
bit3
DA0b3
DA1b3
DA2b3
DA3b3
DA4b3
DA5b3
DA6b3
DA7b3
DA8b3
DA9b3
DA10b3
DA11b3
DA12b3
DA13b3
X
bit2
DA0b2
DA1b2
DA2b2
DA3b2
DA4b2
DA5b2
DA6b2
DA7b2
DA8b2
DA9b2
DA10b2
DA11b2
DA12b2
DA13b2
WDT2
bit1
DA0b1
DA1b1
DA2b1
DA3b1
DA4b1
DA5b1
DA6b1
DA7b1
DA8b1
DA9b1
DA10b1
DA11b1
DA12b1
DA13b1
WDT1
bit0
DA0b0
DA1b0
DA2b0
DA3b0
DA4b0
DA5b0
DA6b0
DA7b0
DA8b0
DA9b0
DA10b0
DA11b0
DA12b0
DA13b0
WDT0
DA0 (r/w) : The output pulse width control for DA0.
DA1 (r/w) : The output pulse width control for DA1.
DA2 (r/w) : The output pulse width control for DA2.
DA3 (r/w) : The output pulse width control for DA3.
DA4 (r/w) : The output pulse width control for DA4.
DA5 (r/w) : The output pulse width control for DA5.
DA6 (r/w) : The output pulse width control for DA6.
DA7 (r/w) : The output pulse width control for DA7.
DA8 (r/w) : The output pulse width control for DA8.
DA9 (r/w) : The output pulse width control for DA9.
DA10 (r/w) : The output pulse width control for DA10.
DA11 (r/w) : The output pulse width control for DA11.
DA12 (r/w) : The output pulse width control for DA12.
DA13 (r/w) : The output pulse width control for DA13.
WDT (w) :
Watchdog timer & special control bit.
DIV253 = 1 The PWM DAC output frequency is (Xtal frequency)/253.
= 0 The PWM DAC output frequency is (Xtal frequency)/256.
*1. All D/A converters are centered with value 80h after power-on.
4/14
MTV012E Revision 1.2 12/23/1998

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MTV012E 전자부품, 판매, 대치품
MYSON
TECHNOLOGY
MTV012E
4.7 H/V Sync Processor Register
Self-Test Patterns (2)
VSYNC
HSYNC
Digital Filter
Present
Check
Vpre
Frequency
Count
Vfreq
Vself
CVSYNC
Polarity
Check
High
Frequency
Mask
Vpol
VBpl
Polarity Check &
Sync Seperator
Present
Check
CVpre
Hself
Hpol
HBpl
Digital Filter
Hpre
Present Check &
Frequency Count Hfreq
VBLANK
HBLANK
H/V SYNC Processor Block Diagram
reg name
PSTUS
HCNTH
HCNTL
VCNTH
VCNTL
PCTR0
PCTR2
P4OUT
INTFLG
INTEN
addr
40h (r)
41h (r)
42h (r)
43h (r)
44h (r)
40h (w)
42h (w)
44h (w)
50h (r/w)
60h (w)
bit7
CVpre
Hovf
HF7
Vovf
VF7
C1
X
X
HPRchg
EHPR
bit6
X
X
HF6
X
VF6
C0
X
X
VPRchg
EVPR
bit5
Hpol
X
HF5
X
VF5
HVsel
X
X
HPLchg
EHPL
bit4
Vpol
X
HF4
X
VF4
STOsel
Selft
X
VPLchg
EVPL
bit3
Hpre
X
HF3
X
VF3
PREFS
STbsh
X
HFchg
EHF
bit2
Vpre
HF10
HF2
X
VF2
HALFV
Rt1
P42
VFchg
EVF
bit1
Hoff
HF9
HF1
X
VF1
HBpl
Rt0
P41
FIFOI
EFIFO
bit0
Voff
HF8
HF0
VF8
VF0
VBpl
STF
P40
MI
EMI
PSTUS (r): The status of polarity, present and static level for HSYNC and VSYNC.
CVpre = 1 The extracted CVSYNC is present.
= 0 The extracted CVSYNC is not present.
Hpol = 1 HSYNC input is positive polarity.
MTV012E Revision 1.2 12/23/1998
7/14

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