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PDF AR629AU9 Data sheet ( Hoja de datos )
| Número de pieza | AR629AU9 | |
| Descripción | Gate Array | |
| Fabricantes | National Semiconductor | |
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MNAR629A-X REV 0A0
MICROCIRCUIT DATA SHEET
Original Creation Date: 06/11/99
Last Update Date: 06/15/99
Last Major Revision Date:
GATE ARRAY (CMOS 1.5u)
General Description
The AR629A Terminal Controller (TC) is a bus interface device (terminal) meeting the
requirements of the ARINC 629 Digital Autonomous Terminal Access Communication databus
specification housing in a 180 CPGA. ARINC 629 is a multiple transmitter, broadcast type,
autonomous terminal access, time division multiplex system that supports deterministic
data communcation over a common single channel transmission medium. The databus protocol
is Carrier Sense/Multiple Access-Clash Avoidance on bus (CS/MA-CA) permitting 100%
utilization of the bus bandwidth during overload conditions. Equal terminal access to the
bus is provided at all times.
Industry Part Number
AR629A-U9MIO
Prime Die
SCX6B150MIO
Controlling Document
5962-9958101QXC
NS Part Numbers
AR629AU9/883
Processing
MIL-STD-883, Method 5004
Quality Conformance Inspection
MIL-STD-883, Method 5005
Subgrp Description
1 Static tests at
2 Static tests at
3 Static tests at
4 Dynamic tests at
5 Dynamic tests at
6 Dynamic tests at
7 Functional tests at
8 Functional tests at
8 Functional tests at
9 Switching tests at
10 Switching tests at
11 Switching tests at
Temp ( oC)
+25
+125
-55
+25
+125
-55
+25
+125
-55
+25
+125
-55
1
1 page  
MNAR629A-X REV 0A0
MICROCIRCUIT DATA SHEET
Electrical Characteristics
AC: SUBSYSTEM READ CHARACTERISTICS(Continued)
(The following conditions apply to all the following parameters, unless otherwise specified.)
AC: Vdd = Vcc = 5V +5%, Vss = GND, -55 C <TA<+125 C, CL = 50pF
SYMBOL
TDBABR
PARAMETER
Time from BUSA
low to BUSR
Tri-State
0 Wait
1 Wait
CONDITIONS
Max Wait
TDBRBA
TDBRQ
TDBSW
TDDS
TDDSBR
TDIO
TDRDSH
BUSR High to BUSA
High Delay
Delay from RICK
to BUSR Low
Time BUSA Low
Prior to RICK
DSO Delay from
RICK
DSO High to BUSR Vdd = 4.75V, Vdd = 5.25V
Tri-State
IOCK high after
rising edge of
RICK
RICK to DSO High Vdd = 4.75V, Vdd = 5.25V
TDRW
THASA
THAW
THDI
THDS
THRW
THWAS
TSDI
TSWA
TWAS
RWO Delay from
RICK
AD Hold Time from Vdd = 4.75V, Vdd = 5.25V
ASO High
Wait Hold after
RICK
Data in Hold
after RICK
DSO Hold after
WAIT
Vdd = 4.75V, Vdd = 5V +5%
RWO Hold after
WAIT
Vdd = 4.75V, Vdd = 5V +5%
ASO Hold after
WAIT
Vdd = 5V +5%
Data Setup Prior
to RICK
WAIT Setup to
RICK
ASO Pulse Width Vdd = 4.75V, Vdd = 5.25V
NOTES
PIN-
NAME
MIN
31
1T-10
1T-20
MAX UNIT
17T+61 nS
SUB-
GROUPS
9, 10,
11
21T+61 nS 9, 10,
11
148T+6 nS
1
9, 10,
11
nS 9, 10,
11
80 nS 9, 10,
11
5T+26 nS 9, 10,
11
80 nS 9, 10,
11
1T+50 nS 9, 10,
11
37 nS 9, 10,
11
1T 1T+40 nS
80 nS
2T-35 2T+40 nS
22 nS
30 nS
5T 9T+30 nS
6T 10T+30 nS
6T 10T+30 nS
30 nS
22 nS
2T-25 2T+25 nS
9, 10,
11
9, 10,
11
9, 10,
11
9, 10,
11
9, 10,
11
9, 10,
11
9, 10,
11
9, 10,
11
9, 10,
11
9, 10,
11
9, 10,
11
5
5 Page 
MNAR629A-X REV 0A0
MICROCIRCUIT DATA SHEET
Electrical Characteristics
AC: INTERNAL REGISTER/TRANSMIT DATA CHARACTERISTICS (Continued)
(The following conditions apply to all the following parameters, unless otherwise specified.)
AC: Vdd = Vcc = 5V +5%, Vss = GND, -55 C <TA<+125 C, CL = 50pF
SYMBOL
TDERR
TDERR
TDFSTAC
TDINT
TDLWM
TDLXIVS
TDRSTAC
TDTXIVS
THXAL
THXAT
TSAX
TSDMA
TWBUSQ
TWBUSQ1
TWXIVS
PARAMETER
CONDITIONS
Delay from BUSQ Vdd = 4.75V, Vdd = 5V +5%
to Error Reg.
Valid (Non NXBA)
BUSQ to error
register valid
(NXBA)
Vdd = 5V +5%
Delay from XIVS
to STAC Low
Vdd = 4.75V, Vdd = 5.25V
Delay from IVR
valid to XIVS
Delay from BUSQ
to LWM valid
Vdd = 5V +5%
Delay from 3rd
bit to leading
XIVS
Vdd = 4.75V, Vdd = 5.25V
Delay from XIVS
to STAC High
Vdd = 4.75V, Vdd = 5.25V
Delay from parity Vdd = 4.75V, Vdd = 5V +5%
bit to trailing
XIVS
AO hold after
leading XIVS
falling edge
Vdd = 5V +5%
AO hold after
Vdd = 4.75V, Vdd = 5.25V
trailing edge of
XIVS falling
AO setup prior to Vdd = 4.75V, Vdd = 5.25V
falling edge of
XIVS
Delay from bit 7 Vdd = 4.75V, Vdd = 5.25V
to DMA start
Width of BUSQ
Vdd = 5V +5%
High during data
sync
BUS Quiet High
during
interstring gap
Vdd = 5V +5%
XIVS pulse Low
width
Vdd = 4.75V, Vdd = 5.25V
NOTES
PIN-
NAME
MIN
15T
MAX
124T
UNIT
nS
SUB-
GROUPS
9, 10,
11
-340T
nS 9, 10,
11
5T-30 5T+35 nS
14T 20T nS
20T nS
3T-35 3T+55 nS
9, 10,
11
9, 10,
11
9, 10,
11
9, 10,
11
2T-30 2T+35 nS
48T 96T nS
9, 10,
11
9, 10,
11
65T nS 9, 10,
11
4T-35
nS 9, 10,
11
2T-35
nS 9, 10,
11
13T-35 13T+60 nS
30T 38T nS
9, 10,
11
9, 10,
11
55T 64T nS 9, 10,
11
2T-10 2T+35 nS 9, 10,
11
11
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet AR629AU9.PDF ] | |
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