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PDF CS3810 Data sheet ( Hoja de datos )
| Número de pieza | CS3810 | |
| Descripción | 32 Qam Demodulator | |
| Fabricantes | Amphion | |
| Logotipo |  |
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CS3810
32 QAM Demodulator
TM
Virtual Components for the Converging World
The CS3810 32 QAM broadband wireless demodulator core has been developed to provide an efficient and
highly optimized solution for wireless data networks. Combined with the CS3710 32 QAM modulator core data
transmission speeds of up to 155Mbps can be achieved at low error rates. The CS3810 is suited for applications
areas such as point-to-point WLAN, metropolitan area networks, wireless VPN and is easily combined with the
CS5200 series of AES cryptography cores to create secure high speed data links.
The CS3810 provides an integrated high performance complete baseband demodulation solution for wireless
data transmission. It includes symbol and timing recovery, adaptive filtering and precise lock tracking to ensure
optimal data recovery under adverse channel conditions. This includes signalling to control AGC and ADC,
ensuring straight forward system integration and deployment. A combined block synchronisation scheme and
error control/ correction system is included to deliver reliable data recovery. The core also includes a
straightforward microprocessor interface allowing the setting of demodulation parameters and easy system
integration.
Data Input
Test Input
Data
Encoding
Error
Protection
Mapping
Spectral Shaping
TXI_OUT
TXQ_OUT
ADC
Control Registers
Test Input
Timing/symbol
recovery
Decode &
Synchronisation
RF RF DAC Filtering
Error Correction Output
& Recovery formatter
Control Registers
Controller/
Processor
CS3710 Broadband Wireless Modulator Core
Controller/
Processor
Data Out
CS3810 Broadband Wireless Demodulator Core
Figure 1: Block Diagram of CS3710/CS3810 Broadband Wireless Modulation/Demodulation Cores
FEATURES
Fully integrated Digital Baseband
demodulator including timing and symbol
recovery and error correction
All digital timing and carrier recovery
Wide carrier tracking range
Acquisition time < 10ms.
Internal DC offset removal
I/Q imbalance adjustment
Programmable equalization adaptation rate
Residual BER better than 10-12
Internal FIFO for smooth data output
Programmable carrier recovery loop
constants and damping factor
Equalizer weights read/write-able from
microprocessor bus
Forward Error Correction Features
Low FEC overhead
Concatenated RS-Convolutional interleaved
system
Interleaver employing the Intelsat method,
with depth of 4
Soft decision based Viterbi decoder, of
constraint length K=7 (64 states)
Input and output start of frame signals
Internal RS correction and Viterbi re-
normalization counters
Data Framing
Intelsat Style Frame/Superframe structure
Superframe detection output sync signals
Amphion continues to expand its family of application-specific cores
See http://www.amphion.com for a current list of products
1
1 page  
TM
Table 1: CS3810 32 QAM Demodulator Interface Signal Descriptions
Name
I/O Width
Description
ERROR CORRECTION STATISTICS
TCMERR
Output
RSERR_U
Output
16
16
RSERR_L
Output
16
AGC CONTROL
AGCP
Output
1
VCO CONTROL
VCOV
Output
12
VCSTRB
Output
ERROR CORRECTION CONTROL
RSERRPRD
Input
UPTCM
Input
BYPASS
Input
LOCK STATUS
AGCOK
Output
LCKBLL
Output
LCKCLL
Output
STATCLL
Output
1
2
8
1
1
1
1
3
FIFOERROR
LCKTCM
LCKUW
Output
Output
Output
1
1
1
Reports the number of estimated errors in the decoded IQ datastream
Reports the number of errors corrected by the Reed Solomon Decoder
(upper 16 bits)
Reports the number of errors corrected by the Reed Solomon Decoder
(lower 16 bits)
AGC width-modulated pulse with period of 256 symbols. The pulse width
is proportional to the input signal level.
VCO control voltage, 12-bit offset-binary format, normalized according to
the VCO frequency range such that the maximal value corresponds to
the lowest frequency and zero corresponds to the highest frequency,
updated every four symbols (9.25 MHz, 8 clock cycles)
VCO control voltage strobe, asserted for 4 cycles in every 8 clock cycles
to indicate the update of VCOV
Static signal-sets the duration over which RS statistics are gathered
Static signal used to control operation of TCM decoder
Static signal, when asserted the TCM decoder is bypassed
AGC OK indicator, asserted when the average peak sample level is
within +/-15% of the ideal level
BLL lock flag, asserted when lock is declared or retained, updated once
every BLL lock detection window
CLL lock flag, asserted when lock is declared or retained, updated for
every output symbol (two clock cycles)
CLL status, updated for every output symbol (two clock cycles)
000: idle (equalizer in initial mode, phase error set to 0)
001: initial (equalizer in CMA, phase error set to 0)
010: AFC (equalizer in CMA, estimate frequency offset)
011: DFS (equalizer in CMA, scan counter increases)
100: 4GC pull-in (equalizer in CMA, CLL 4GC pull-in)
110: DD pull-in (equalizer in CMA, CLL DD pull-in)
111: Lock (equalizer in DD, CLL DD tracking)
When Asserted signifies the output fifo has overflowed and data has
been dropped
When asserted signifies the TCM decoder has achieved lock
When asserted signifies that block synchronization has been achieved
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5 Page 
Typical ASIC or FPGA Design Flow
(Conceptual)
System-Level "C" Code simulation
Hardware RTL Development
RTL Simulation
Logic Synthesis
Gate-level analysis
(timing & functional)
Physical Design
Figure 8: Design Data Formats Supplied by Amphion
Data Formats
Supplied by AMPHION
Bit Accurate
C Model
TM
RTL Simulation
Models
Testbench
(VHDL & Verilog)
Netlists
(Verilog, VHDL, EDIF, .bd)
FPGA Programming
Files
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet CS3810.PDF ] | |
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