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부품번호 XC18Vxxx 기능
기능 In-System Programmable Configuration PROMs
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XC18Vxxx 데이터시트, 핀배열, 회로
0
R
DS026 (v4.0) June 11, 2003
00
Features
• In-system programmable 3.3V PROMs for
configuration of Xilinx FPGAs
- Endurance of 20,000 program/erase cycles
- Program/erase over full commercial/industrial
voltage and temperature range (–40°C to +85°C)
• IEEE Std 1149.1 boundary-scan (JTAG) support
• Simple interface to the FPGA
• Cascadable for storing longer or multiple bitstreams
• Low-power advanced CMOS FLASH process
XC18V00 Series In-System
Programmable Configuration
PROMs
Product Specification
• Dual configuration modes
- Serial Slow/Fast configuration (up to 33 MHz)
- Parallel (up to 264 Mb/s at 33 MHz)
• 5V tolerant I/O pins accept 5V, 3.3V and 2.5V signals
• 3.3V or 2.5V output capability
• Available in PC20, SO20, PC44, and VQ44 packages
• Design support using the Xilinx Alliance and
Foundation series software packages.
• JTAG command initiation of standard FPGA
configuration
Description
Xilinx introduces the XC18V00 series of in-system program-
mable configuration PROMs (Figure 1). Devices in this 3.3V
family include a 4-megabit, a 2-megabit, a 1-megabit, and a
512-kilobit PROM that provide an easy-to-use, cost-effec-
tive method for re-programming and storing Xilinx FPGA
configuration bitstreams.
When the FPGA is in Master Serial mode, it generates a
configuration clock that drives the PROM. A short access
time after CE and OE are enabled, data is available on the
PROM DATA (D0) pin that is connected to the FPGA DIN
pin. New data is available a short access time after each ris-
ing clock edge. The FPGA generates the appropriate num-
ber of clock pulses to complete the configuration. When the
FPGA is in Slave Serial mode, the PROM and the FPGA
are clocked by an external clock.
CLK CE
When the FPGA is in Master-SelectMAP mode, the FPGA
generates a configuration clock that drives the PROM.
When the FPGA is in Slave-Parallel or Slave-SelectMAP
Mode, an external oscillator generates the configuration
clock that drives the PROM and the FPGA. After CE and
OE are enabled, data is available on the PROMs DATA
(D0-D7) pins. New data is available a short access time
after each rising clock edge. The data is clocked into the
FPGA on the following rising edge of the CCLK. A free-run-
ning oscillator can be used in the Slave-Parallel or
Slave-SelecMAP modes.
Multiple devices can be concatenated by using the CEO
output to drive the CE input of the following device. The
clock inputs and the DATA outputs of all PROMs in this
chain are interconnected. All devices are compatible and
can be cascaded with other members of the family or with
the XC17V00 one-time programmable Serial PROM family.
OE/Reset
TCK
TMS
TDI
TDO
Control
and
JTAG
Interface
Data
Address
Memory
Data
Serial
or
Parallel
Interface
CEO
D0 DATA
Serial or Parallel Mode
7
D[1:7]
Parallel Interface
CF
Figure 1: XC18V00 Series Block Diagram
DS026_01_090502
©2003 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and further disclaimers are as listed at http://www.xilinx.com/legal.htm. All other
trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this fea-
ture, application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you
may require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any war-
ranties or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose.
DS026 (v4.0) June 11, 2003
Product Specification
www.xilinx.com
1-800-255-7778
1




XC18Vxxx pdf, 반도체, 판매, 대치품
XC18V00 Series In-System Programmable Configuration PROMs
Pinout Diagrams
NC
NC
TDI
NC
TMS
GND
TCK
VCCO
D4
CF
NC
7
8
9
10
11
12
13
14
15
16
17
PC44
Top View
39 NC
38 NC
37 TDO
36 NC
35 D1
34 GND
33 D3
32 VCCO
31 D5
30 NC
29 NC
DATA(D0)
D2
CLK
TDI
TMS
TCK
CF/D4*
OE/RESET
D6
CE
1
2
3
4
5 SO20
6 Top
7 View
8
9
10
20
19
18
17
16
15
14
13
12
11
VCCINT*
VCCO
VCCINT*
TDO
D1
D3
D5
CEO
D7
GND
*See pin descriptions.
DS026_14_060403
R
*See pin descriptions.
DS026_12_060403
TDI
TMS
TCK
D4/CF*
OE/RESET
4 18
5 PC20 17
6 Top View 16
7 15
8 14
*See pin descriptions.
VCCINT*
TDO
D1
D3
D5
DS026_15_060403
NC
NC
TDI
NC
TMS
GND
TCK
VCCO
D4
CF
NC
1
2
3
4
5
6
7
8
9
10
11
VQ44
Top View
33 NC
32 NC
31 TDO
30 NC
29 D1
28 GND
27 D3
26 VCCO
25 D5
24 NC
23 NC
*See pin descriptions.
DS026_13_060403
4
www.xilinx.com
DS026 (v4.0) June 11, 2003
1-800-255-7778
Product Specification

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XC18Vxxx 전자부품, 판매, 대치품
R XC18V00 Series In-System Programmable Configuration PROMs
The read security bit can be set by the user to prevent the
internal programming pattern from being read or copied via
JTAG. When set, it allows device erase. Erasing the entire
device is the only way to reset the read security bit.
Table 3: Data Security Options
Default = Reset
Read Allowed
Program/Erase Allowed
Verify Allowed
Set
Read Inhibited via JTAG
Program/Erase Allowed
Verify Inhibited
IEEE 1149.1 Boundary-Scan (JTAG)
The XC18V00 family is fully compliant with the IEEE Std.
1149.1 Boundary-Scan, also known as JTAG. A Test
Access Port (TAP) and registers are provided to support all
required boundary scan instructions, as well as many of the
optional instructions specified by IEEE Std. 1149.1. In addi-
tion, the JTAG interface is used to implement in-system pro-
gramming (ISP) to facilitate configuration, erasure, and
verification operations on the XC18V00 device.
Table 4 lists the required and optional boundary-scan
instructions supported in the XC18V00. Refer to the IEEE
Std. 1149.1 specification for a complete description of
boundary-scan architecture and the required and optional
instructions.
Table 4: Boundary Scan Instructions
Boundary-Scan Binary
Command Code [7:0]
Description
Required Instructions
BYPASS
11111111 Enables BYPASS
SAMPLE/
PRELOAD
00000001 Enables boundary-scan
SAMPLE/PRELOAD operation
EXTEST
00000000
Optional Instructions
CLAMP
11111010
Enables boundary-scan
EXTEST operation
Enables boundary-scan
CLAMP operation
HIGHZ
11111100 all outputs in high-impedance
state simultaneously
IDCODE
11111110 Enables shifting out
32-bit IDCODE
USERCODE
11111101 Enables shifting out
32-bit USERCODE
XC18V00 Specific Instructions
CONFIG
11101110 Initiates FPGA configuration
by pulsing CF pin Low once
Instruction Register
The Instruction Register (IR) for the XC18V00 is eight bits
wide and is connected between TDI and TDO during an
instruction scan sequence. In preparation for an instruction
scan sequence, the instruction register is parallel loaded
with a fixed instruction capture pattern. This pattern is
shifted out onto TDO (LSB first), while an instruction is
shifted into the instruction register from TDI. The detailed
composition of the instruction capture pattern is illustrated
in Figure 3.
The ISP Status field, IR(4), contains logic 1if the device is
currently in ISP mode; otherwise, it contains logic 0. The
Security field, IR(3), contains logic 1if the device has been
programmed with the security option turned on; otherwise, it
contains logic 0.
IR[7:5] IR[4] IR[3] IR[2] IR[1:0]
TDI-> 0 0 0 ISP Security
Status
0
0 1 ->TDO
Notes:
1. IR(1:0) = 01 is specified by IEEE Std. 1149.1
Figure 3: Instruction Register Values Loaded into IR as
Part of an Instruction Scan Sequence
Boundary Scan Register
The boundary-scan register is used to control and observe
the state of the device pins during the EXTEST, SAM-
PLE/PRELOAD, and CLAMP instructions. Each output pin
on the XC18V00 has two register stages that contribute to
the boundary-scan register, while each input pin only has
one register stage.
For each output pin, the register stage nearest to TDI con-
trols and observes the output state, and the second stage
closest to TDO controls and observes the High-Z enable
state of the pin.
For each input pin, the register stage controls and observes
the input state of the pin.
Identification Registers
The IDCODE is a fixed, vendor-assigned value that is used
to electrically identify the manufacturer and type of the
device being addressed. The IDCODE register is 32 bits
wide. The IDCODE register can be shifted out for examina-
tion by using the IDCODE instruction. The IDCODE is avail-
able to any other system component via JTAG.
The IDCODE register has the following binary format:
vvvv:ffff:ffff:aaaa:aaaa:cccc:cccc:ccc1
where
v = the die version number
f = the family code (50h for XC18V00 family)
a = the ISP PROM product ID (36h for the XC18V04)
c = the company code (49h for Xilinx)
Note: The LSB of the IDCODE register is always read as
logic 1as defined by IEEE Std. 1149.1.
DS026 (v4.0) June 11, 2003
Product Specification
www.xilinx.com
1-800-255-7778
7

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In-System Programmable Configuration PROMs

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