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PDF CY8C29666 Data sheet ( Hoja de datos )
| Número de pieza | CY8C29666 | |
| Descripción | Programmable System-on-Chip | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY8C29466/CY8C29566
CY8C29666/CY8C29866
PSoC® Programmable System-on-Chip™
PSoC® Programmable System-on-Chip™
Features
■ Powerful Harvard-architecture processor
❐ M8C processor speeds to 24 MHz
❐ Two 8 × 8 multiply, 32-bit accumulate
❐ Low power at high speed
❐ Operating voltage: 3.0 V to 5.25 V
❐ Operating voltages down to 1.0 V using on-chip switch mode
pump (SMP)
❐ Industrial temperature range: –40 °C to +85 °C
■ Advanced peripherals (PSoC® blocks)
❐ 12 rail-to-rail analog PSoC blocks provide:
• Up to 14-bit analog-to-digital converters (ADCs)
• Up to 9-bit digital-to-analog converters (DACs)
• Programmable gain amplifiers (PGAs)
• Programmable filters and comparators
❐ 16 digital PSoC blocks provide:
• 8- to 32-bit timers and counters, 8- and 16-bit pulse-width
modulators (PWMs)
• Cyclical redundancy check (CRC) and pseudo random
sequence (PRS) modules
• Up to four full-duplex universal asynchronous receiver
transmitters (UARTs)
• Multiple serial peripheral interface (SPI) masters or slaves
• Can connect to all general-purpose I/O (GPIO) pins
❐ Create complex peripherals by combining blocks
■ Precision, programmable clocking
❐ Internal ±5% [1] 24- / 48-MHz main oscillator
❐ 24- / 48-MHz with optional 32.768 kHz crystal
❐ Optional external oscillator, up to 24 MHz
❐ Internal oscillator for watchdog and sleep
■ Flexible on-chip memory
❐ 32 KB flash program storage 50,000 erase/write cycles
❐ 2 KB static random access memory (SRAM) data storage
❐ In-system serial programming (ISSP)
❐ Partial flash updates
❐ Flexible protection modes
❐ Electrically erasable programmable read-only memory
(EEPROM) emulation in flash
■ Programmable pin configurations
❐ 25-mA sink, 10-mA source on all GPIOs
❐ Pull-up, pull-down, high Z, strong, or open-drain drive modes
on all GPIOs
❐ Eight standard analog inputs on GPIOs, plus four additional
analog inputs with restricted routing
❐ Four 40 mA analog outputs on GPIOs
❐ Configurable interrupt on all GPIOs
■ Additional system resources
❐ I2C slave, master, and multi-master to 400 kHz
❐ Watchdog and sleep timers
❐ User-configurable low-voltage detection (LVD)
❐ Integrated supervisory circuit
❐ On-chip precision voltage reference
■ Complete development tools
❐ Free development software (PSoC Designer™)
❐ Full-featured in-circuit emulator (ICE) and
programmer
❐ Full-speed emulation
❐ Complex breakpoint structure
❐ 128 KB trace memory
❐ Complex events
❐ C compilers, assembler, and linker
Logic Block Diagram
PSoC
CORE
Port Port Port Port Port Port Port Port 0 with
7 6 5 4 3 2 1 Analog Drivers
System Bus
Global Digital Interconnect
Global Analog Interconnect
SRAM
2 KB
SROM Flash 32KB
Interrupt
Controller
CPU Core (M8C)
Sleep and
Watchdog
Multiple Clock Sources
(Includes IMO, ILO, PLL, and ECO)
DIGITAL SYSTEM
Digital
Block
Array
ANALOG SYSTEM
Analog
Block
Array
Analog
Ref.
Analog
Input
Muxing
Digital
Clocks
Multiply
Accum.
Decimator
POR and LVD Internal
I2C Voltage
System Resets Ref.
SYSTEM RESOURCES
Switch
Mode
Pump
Errata: For information on silicon errata, see “Errata” on page 61. Details include trigger conditions, devices affected, and proposed workaround.
Note
1. Errata: When the device is operated within 0 °C to 70 °C, the frequency tolerance is reduced to ±2.5%, but if operated at extreme temperature (below 0 °C or above
70 °C), frequency tolerance deviates from ±2.5% to ±5%. For more information, see Errata on page 61.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-12013 Rev. AB
• San Jose, CA 95134-1709 • 408-943-2600
Revised August 12, 2015
1 page  
CY8C29466/CY8C29566
CY8C29666/CY8C29866
Digital peripheral configurations include:
■ PWMs (8- and 16-bit)
■ PWMs with dead band (8- and 16-bit)
■ Counters (8- to 32-bit)
■ Timers (8- to 32-bit)
■ UART 8-bit with selectable parity (up to 2)
■ SPI slave and master (up to 2)
■ I2C slave and multi-master (one available as a system
resource)
■ CRC generator (8- to 32-bit)
■ IrDA (up to 2)
■ PRS generators (8- to 32-bit)
The digital blocks can be connected to any GPIO through a
series of global buses that can route any signal to any pin. The
buses also allow for signal multiplexing and for performing logic
operations. This configurability frees your designs from the
constraints of a fixed peripheral controller.
Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This allows you the
optimum choice of system resources for your application. Family
resources are shown in the table titled “PSoC Device
Characteristics” on page 6.
Analog System
The analog system is composed of 12 configurable blocks, each
containing an opamp circuit that allows the creation of complex
analog signal flows. Analog peripherals are very flexible and can
be customized to support specific application requirements.
Some of the more common PSoC analog functions (most
available as user modules) are:
■ ADCs (up to 4, with 6- to 14-bit resolution; selectable as
incremental, delta sigma, and SAR)
■ Filters (2-, 4-, 6-, and 8-pole band pass, low pass, and notch)
■ Amplifiers (up to 4, with selectable gain to 48x)
■ Instrumentation amplifiers (up to 2, with selectable gain to 93x)
■ Comparators (up to 4, with 16 selectable thresholds)
■ DACs (up to 4, with 6-bit to 9-bit resolution)
■ Multiplying DACs (up to 4, with 6-bit to 9-bit resolution)
■ High current output drivers (four with 30-mA drive as a core
resource)
■ 1.3-V reference (as a system resource)
■ DTMF Dialer
■ Modulators
■ Correlators
■ Peak detectors
■ Many other topologies possible
Analog blocks are provided in columns of three, which includes
one continuous time (CT) and two switched capacitor (SC)
blocks, as shown in Figure 3.
Figure 3. Analog System Block Diagram
P0[7]
P0[6]
P0[5]
P0[4]
P0[3]
P0[1]
P0[2]
P0[0]
P2[3]
P2[1]
P2[6]
P2[4]
P2[2]
P2[0]
Array Input Configuration
ACI0[1:0] ACI1[1:0]
ACI2[1:0] ACI3[1:0]
ACB00
Block Array
ACB01
ACB02
ACB03
ASC10
ASD11
ASC12
ASD13
ASD20
ASC21
ASD22
ASC23
Interface to
Digital System
Ref Hi
Ref Lo
AGND
Analog Reference
Re fe r e nce
Ge ne r ator s
AGNDIn
Ref In
Bandgap
M8C Interface (Address Bus, Data Bus, Etc.)
Document Number: 38-12013 Rev. AB
Page 5 of 67
5 Page 
CY8C29466/CY8C29566
CY8C29666/CY8C29866
44-Pin Part Pinout
Table 3. 44-Pin Part Pinout (TQFP)
Pin Type
Pin
No. Digital Analog Name
Description
1 I/O
P2[5]
2 I/O
I P2[3] Direct switched capacitor block input
3 I/O
I P2[1] Direct switched capacitor block input
4 I/O
P4[7]
5 I/O
P4[5]
6 I/O
P4[3]
7 I/O
P4[1]
8
Power
SMP Switch mode pump (SMP) connection to
external components required
9 I/O
P3[7]
10 I/O
P3[5]
11 I/O
P3[3]
12 I/O
13 I/O
14 I/O
P3[1]
P1[7]
P1[5]
I2C SCL
I2C SDA
15 I/O
16 I/O
P1[3]
P1[1]
Crystal (XTALin), I2C SCL, ISSP-SCLK[6]
17 Power
18 I/O
VSS
P1[0]
Ground connection
Crystal (XTALout), I2C SDA, ISSP-SDATA[6]
19 I/O
P1[2]
20 I/O
P1[4] Optional EXTCLK
21 I/O
P1[6]
22 I/O
P3[0]
23 I/O
P3[2]
24 I/O
P3[4]
25 I/O
P3[6]
26
Input
XRES Active high external reset with internal
pull-down
27 I/O
P4[0]
28 I/O
P4[2]
29 I/O
P4[4]
30 I/O
P4[6]
31 I/O
I P2[0] Direct switched capacitor block input
32 I/O
I P2[2] Direct switched capacitor block input
33 I/O
P2[4] External analog ground (AGND)
34 I/O
P2[6] External voltage reference (VREF)
35 I/O
I P0[0] Analog column mux input
36 I/O
I/O P0[2] Analog column mux input and column output
37 I/O
I/O P0[4] Analog column mux input and column output
38 I/O
I P0[6] Analog column mux input
39
Power
VDD Supply voltage
40 I/O
I P0[7] Analog column mux input
41 I/O
I/O P0[5] Analog column mux input and column output
42 I/O
I/O P0[3] Analog column mux input and column output
43 I/O
I P0[1] Analog column mux input
44 I/O
P2[7]
LEGEND: A = Analog, I = Input, and O = Output.
Figure 5. CY8C29566 44-Pin PSoC Device
P2[5]
A, I, P2[3]
A, I, P2[1]
P4[7]
P4[5]
P4[3]
P4[1]
SMP
P3[7]
P3[5]
P3[3]
1
2
3
4
5
6
7
8
9
10
11
TQFP
33 P2[4], External AGND
32 P2[2], A, I
31 P2[0], A, I
30 P4[6]
29 P4[4]
28 P4[2]
27 P4[0]
26 XRES
25 P3[6]
24 P3[4]
23 P3[2]
Note
6. These are the ISSP pins, which are not High Z at POR. See the PSoC Programmable System-on-Chip Technical Reference Manual for details.
Document Number: 38-12013 Rev. AB
Page 11 of 67
11 Page | ||
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| PDF Descargar | [ Datasheet CY8C29666.PDF ] | |
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