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PDF MT9041 Data sheet ( Hoja de datos )
| Número de pieza | MT9041 | |
| Descripción | Multiple Output Trunk PLL | |
| Fabricantes | Mitel Networks Corporation | |
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MT9041
®
Multiple Output Trunk PLL
Advance Information
Features
• Provides T1 and E1 clocks, and ST-BUS/GCI
framing signals locked to an input reference of
either 8 kHz (frame pulse), 1.544 MHz (T1), or
2.048 MHz (E1)
• Meets AT & T TR62411 and ETSI ETS 300 011
specifications for a 1.544 MHz (T1), or
2.048 MHz (E1) input reference
• Typical unfiltered intrinsic output jitter is
0.013 UI peak-to-peak
• Jitter attenuation of 15 dB @ 10 Hz,
34 dB @ 100 Hz and 50 dB @ 5 to 40 kHz
• Low power CMOS technology
Applications
• Synchronization and timing control for T1 and
E1 digital transmission links
• ST-BUS clock and frame pulse sources
• Primary Trunk Rate Converters
ISSUE 1
May 1995
Ordering Information
MT9041AP
28 Pin PLCC
-40°C to +85°C
Description
The MT9041 is a digital phase-locked loop (PLL)
designed to provide timing and synchronization
signals for T1 and E1 primary rate transmission links
that are compatible with ST-BUS/GCI frame
alignment timing requirements. The PLL outputs can
be synchronized to either a 2.048 MHz, 1.544 MHz,
or 8 kHz reference. The T1 and E1 outputs are fully
compliant with AT & T TR62411 (ACCUNET® T1.5)
and ETSI ETS 300 011 intrinsic jitter and jitter
transfer specifications, respectively, when
synchronized to primary reference input clock rates
of either 1.544 MHz or 2.048 MHz.
The PLL also provides additional high speed output
clocks at rates of 3.088 MHz, 4.096 MHz, 8.192
MHz, and 16.384 MHz for backplane synchro-
nization.
VDD VSS
PRI Phase
Detector
Loop
Filter
IC0
IC1
Mode
Select
MCLKo
MCLKi
DCO
Interface
Circuit
Divider
C3
C1.5
C16
C8
C4
C2
F0o
FP8-STB
FP8-GCI
MS FSEL1 FSEL2
Figure 1 - Functional Block Diagram
3-83
1 page  
Advance Information
MT9041
Freerun Accuracy
Jitter Transfer Function
The Freerun accuracy of the PLL is a measure of
how accurately the PLL can reproduce the desired
output frequency. The freerun accuracy is a function
of master clock frequency which must be 20 MHz
±32 ppm in order to meet AT & T TR62411 and ETSI
specifications.
Jitter Performance
The output jitter of a digital trunk PLL is composed of
intrinsic jitter, measured using a jitter free reference
clock, and frequency dependent jitter, measured by
applying known levels of jitter on the references
clock. The jitter spectrum indicates the frequency
content of the output jitter.
Intrinsic Jitter
Intrinsic jitter is the jitter added to an output signal by
the processing device, in this case the enhanced
PLL. Tables 3 and 4 show the average measured
intrinsic jitter of the T1 and E1 outputs. Each
measurement is an average based upon a ±100 ppm
deviation (in steps of 20 ppm) on the input reference
clock. Jitter on the master clock will increase intrinsic
jitter of the device, hence attention to minimization of
master clock jitter is required.
The jitter transfer function is a measure of the
transfer characteristics of the PLL to frequency
specific jitter on the referenced input of the PLL. It is
directly linked to the loop bandwidth and the
magnitude of the phase error suppression
characteristics of the PLL. It is measured by applying
jitter of specific magnitude and frequencies to the
input of the PLL, then measuring the magnitude of
the output jitter (both filtered and unfiltered) on the
T1 or E1 output.
Care must be taken when measuring the transfer
characteristics to ensure that critical jitter alias
frequencies are included in the measurement (i.e.,
for digital phase locked loops using an 8 kHz input).
Tables 5 and 6 provide measured results for the jitter
transfer characteristics of the PLL for both a 1.544
MHz and 2.048 MHz reference input clock. The
transfer characteristics for an 8 kHz reference input
will be the same.
Figures 4 and 5 show the jitter attenuation
performance of the T1 and E1 outputs plotted
against AT & T TR62411 and ETSI requirements,
respectively.
Output Jitter in UIp-p
Reference Input
FLT0 Unfiltered
FLT1
10Hz - 8kHz
FLT2
10Hz - 40kHz
FLT3
8kHz - 40kHz
8 kHz
1.544 MHz
.011
.011
.004
.001
.006
.002
.002
.001
2.048 MHz
.011
.001
.002
.001
Table 3 -Typical Intrinsic Jitter for the T1 Output
Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
Output Jitter in UIp-p
Reference Input
FLT0 Unfiltered
FLT1
20Hz - 100kHz
FLT2
700Hz - 100kHz
8 kHz
1.544 MHz
2.048 MHz
.011
.011
.011
.002
.002
.002
.002
.002
.002
Table 4 - Typical Intrinsic Jitter for the E1 Output
Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
3-87
5 Page 
Advance Information
MT9041
AC Electrical Characteristics (see Fig. 6)†-Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics
Sym
Min Typ‡ Max Units Test Conditions
31 C4 clock period
32 C4 clock output rise time
33 C4 clock output fall time
34 O C4 clock output duty cycle
35
U
T
C8 clock period
36 P C8 clock output rise time
U
37 T C8 clock output fall time
38 S C8 clock output duty cycle
tP-C4
tRC4
tFC4
tP-C8
tRC8
tFC8
244
59
59
50
122
59
59
50
ns
ns Load = 85pF
ns Load = 85pF
%
ns
ns Load = 85pF
ns Load = 85pF
%
39 C16 clock period
40 C16 clock output rise time
41 C16 clock output fall time
42 C16 clock output duty cycle
tP-C16
tRC16
tFC16
61 ns
5 9 ns Load = 85pF
5 9 ns Load = 85pF
43 50 55
%
Duty cycle on
MCLKi =50%
† -Timing is over recommended temperature & power supply voltages.
‡ -Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
3-93
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet MT9041.PDF ] | |
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