Datasheet.kr   

ID82C85 데이터시트 PDF




Intersil Corporation에서 제조한 전자 부품 ID82C85은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 ID82C85 자료 제공

부품번호 ID82C85 기능
기능 CMOS Static Clock Controller/Generator
제조업체 Intersil Corporation
로고 Intersil Corporation 로고


ID82C85 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.




전체 20 페이지수

미리보기를 사용할 수 없습니다

ID82C85 데이터시트, 핀배열, 회로
82C85
March 1997
CMOS Static Clock Controller/Generator
Features
Description
• Generates the System Clock For CMOS or NMOS
Microprocessors and Peripherals
• Complete Control Over System Operation for Very
Low System Power
- Stop-Oscillator
- Low Frequency
- Stop-Clock
- Full Speed Operation
• DC to 25MHz Operation (DC to 8MHz System Clock)
• Generates 50% and 33% Duty Cycle Clocks
(Synchronized)
• Uses a Parallel Mode Crystal Circuit or External
Frequency Source
• TTL Compatible Inputs/Outputs
• 24 Lead Slimline Dual-In-Line or 28 Pad Square LCC
Package Options
• Single 5V Power Supply
• Operating Temperature Range
- C82C85 . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to +70oC
- I82C85 . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC
- M82C85 . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
Ordering Information
PART NUMBER
CS82C85
IS82C85
CD82C85
ID82C85
MD82C85/B
MR82C85/B
PACKAGE
28 Ld PLCC
24 Ld CERDIP
28 Pad CLCC
TEMP. RANGE
0oC to +70oC
-40oC to +85oC
0oC to +70oC
-40oC to +85oC
-55oC to +125oC
-55oC to +125oC
PKG. NO.
N28.45
N28.45
F24.3
F24.3
F24.3
J28.A
The Intersil 82C85 Static CMOS Clock Controller/Genera-
tor provides complete control of static CMOS system oper-
ating modes and supports full speed, slow, stop-clock and
stop-oscillator operation. While directly compatible with the
Intersil 80C86 and 80C88 16-bit Static CMOS Microproces-
sor Family, the 82C85 can also be used for general system
clock control.
For static system designs, separate signals are provided on
the 82C85 for stop (S0, S1, S2/STOP) and start (START)
control of the crystal oscillator and system clocks. A single
control line (SLO/FST) determines 82C85 fast (crystal/EFI
frequency divided by 3) or slow (crystal/EFI frequency
divided by 768) mode operation. Automatic maximum
mode 80C86 and 80C88 software HALT instruction decode
logic in the 82C85 enables software-based clock control.
Restart logic insures valid clock start-up and complete syn-
chronization of system clocks.
The 82C85 is manufactured using the Intersil advanced
Scaled SAJI IV CMOS process. In addition to clock control
circuitry, the 82C85 also contains a crystal controlled
oscillator (up to 25MHz), clock generation logic, complete
“Ready” synchronization and reset logic. This permits the
designer to tailor the system power-performance product to
provide optimum performance at low power levels.
Pinouts
24 LEAD CERDIP
TOP VIEW
CSYNC 1
PCLK 2
AEN1 3
RDY1 4
READY 5
RDY2 6
AEN2 7
CLK 8
GND 9
CLK50 10
START 11
SLO/FST 12
24 VCC
23 X1
22 X2
21 ASYNC
20 EFI
19 F/C
18 OSC
17 RES
16 RESET
15 S2/STOP
14 S1
13 S0
28 LEAD PLCC, CLCC
TOP VIEW
4 3 2 1 28 27 26
RDY1 5
25 NC
READY 6
24 ASYNC
RDY2 7
23 EFI
AEN2 8
22 F/C
CLK 9
21 OSC
GND 10
20 RES
NC 11
19 RESET
12 13 14 15 16 17 18
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
4-297
File Number 2976.1




ID82C85 pdf, 반도체, 판매, 대치품
82C85
Functional Description
The 82C85 Static Clock Controller/Generator provides sim-
ple and complete control static CMOS system operating
modes. The 82C85 supports full speed, slow, stop-clock and
stop-oscillator operation. While it is directly compatible with
the Intersil 80C86 and 80C88 CMOS 16-bit static micropro-
cessors, the 82C85 can also be used for general purpose
system clock control.
The 82C85 pinout is a superset of the 82C84A Clock Gener-
ator/Driver. 82C85 pins 1-9, 16-24 are compatible with
82C84A pins 1-9, 10-18 respectively. An 82C84A can be
placed in the upper 18 pins of an 82C85 socket and it will
operate correctly (without the ability to control the clock and
oscillator operation.) This allows dual design for simple sys-
tem upgrades. The 82C85 will also emulate an 82C84A
when pins 11-15 on the 82C85 are tied to VCC.
For static systems designs, separate signals are provided on
the 82C85 for stop and start control of the crystal oscillator
and clock outputs. A single control line determines 82C85
fast (crystal/EFI frequency divided by 3) or slow (crystal/EFI
frequency divided by 768) mode operation. The 82C85 also
contains a crystal controlled oscillator, clock generation
logic, complete “Ready” synchronization and reset logic.
Automatic 80C86/88 software HALT instruction decode logic
is present to ease the design of software-based clock control
systems and provide complete software control of STOP
mode operation. Restart logic insures valid clock start-up
and complete synchronization of CLK, CLK50 and PCLK.
Static Operating Modes
In static CMOS system design, there are four basic operat-
ing modes. The 82C85 Static Clock Controller supports each
of them. These modes are: FAST, SLOW, STOP-CLOCK
and STOP-OSCILLATOR. Each has distinct power and per-
formance characteristics which can be matched to the needs
of a particular system at a specific time (See Table 1).
Keep in mind that a single system may require all of these
operating modes at one time or another during normal opera-
tion. A design need not be limited to a single operating mode
or a specific combination of modes. The appropriate operating
mode can be matched to the power-performance level
needed at a specific time or in a particular circumstance.
Reset Logic
The 82C85 reset logic provides a Schmitt trigger input (RES)
and a synchronizing flip-flop to generate the reset timing.
The reset signal is synchronized to the falling edge of CLK. A
simple RC network can be used to provide power-on reset
by utilizing this function of the 82C85.
When in the crystal oscillator (F/C = LOW) or the EFI (F/C =
HIGH) mode, a LOW state on the RES input will set the
RESET output to the HIGH state. It will also restart the oscil-
lator circuit if it is in the idle state. The RESET output is guar-
anteed to stay in the HIGH state for a minimum of 16 CLK
cycles after a low-to-high transition of the RES input.
An oscillator restart count sequence will not be disturbed by
RESET if this count is already in progress. After the restart
counter expires, the RESET output will stay HIGH at least for
16 periods of CLK before going LOW. RESET can be kept high
beyond this time by a continuing low input on the RES input.
If F/C is low (crystal oscillator mode), a low state on RES
starts the crystal oscillator circuit. The stopped outputs
remain inactive, until the oscillator signal amplitude reaches
the X1 Schmitt trigger input threshold voltage and 8192
cycles of the crystal oscillator output are counted by an inter-
nal counter. After this count is complete, the stopped outputs
(CLK, CLK50, PCLK, and OSC) start cleanly with the proper
phase relationships.
This 8192 count requirement insures that the CLK, CLK50
and PCLK outputs will meet minimum clock requirements
and will not be affected by unstable oscillator characteristics
which may exist during the oscillator start-up sequence. This
sequence is also followed when a START command is
issued while the 82C85 oscillator is stopped.
Oscillator/Clock Start Control
Once the oscillator is stopped (or committed to stop) or at power-
on, the restart sequence is initiated by a HIGH state on START or
LOW state on RES. If F/C is HIGH, then restart occurs immedi-
ately after the START or RES input is synchronized internally.
This insures that stopped outputs (CLK, PCLK, OSC and
CLK50) start cleanly with the proper phase relationship.
If F/C is low (crystal oscillator mode), a HIGH state on the
START input or a low state on RES causes the crystal oscil-
lator to be restarted. The stopped outputs remain stopped,
TABLE 1. STATIC SYSTEM OPERATING MODE CHARACTERISTICS
OPERATING
MODE
DESCRIPTION
POWER LEVEL
PERFORMANCE
Stop-Oscillator All system clocks and main clock oscillator are
stopped
Maximum Savings
Slowest response due to oscillator
restart time
Stop-Clock
System CPU and peripherals clocks stop but main
clock oscillator continues to run at rated frequency
Reduced System
Power
Fast restart-no oscillator restart time
Slow
System CPU clocks are slowed while peripheral clock Power Dissipation
and main clock oscillator run at rated frequency
Slightly Higher Than
Stop-Clock
Continuous operation at low frequency
Fast
All clocks and oscillators run at rated frequency
Highest Power
Fastest response
4-300

4페이지










ID82C85 전자부품, 판매, 대치품
82C85
The 82C85 S2/STOP, S1 and S0 control lines were designed
to detect a passive 111 state followed by a HALT 011 logic
state before recognizing the HALT instruction and stopping
the system clocks. In the MAXimum mode, the 80C86/88
status lines go into a passive (no bus cycle) logic 111 state
prior to executing a HALT instruction. The qualification of a
passive no bus cycle logic 111 state insures that random
transitions of the status lines into a logic 011 state will not
stop the system clock. This is necessary since the status
lines of the 80C86/88 transition through an unknown state
during T3 of the bus cycle.
Once the HALT instruction is decoded by the 82C85, either
the oscillator is stopped (STOP-OSCILLATOR mode F/C tied
low) or the external frequency source is gated off internally
(STOP-CLOCK mode F/C HIGH). When the HALT instruc-
tion is decoded with F/C low, the CLK and CLK50 will be
stopped in a logic high state after 2 additional cycles of the
clock. PCLK stops in it’s current state (high or low). This is
true for both SLOW and FAST mode operation. The HALT
instruction is detected in the same manner whether the
82C85 is in the SLOW or FAST mode.
Independent Stop Control for Minimum Mode Operation
When the 80C86 and 80C88 microprocessors are config-
ured in MINimum Mode (MN/MX pin tied high), their status
lines S0, S1, and S2 assume alternate functions. The logic
states and sequences (passive before a HALT) necessary
for automatic HALT detect in the 82C85 do not occur as in
the MAXimum mode. The 82C85 controller cannot use the
microprocessor status lines to detect a software Halt instruc-
tion when operating in MINimum mode.
However, the negative edge-activated S2/STOP pin provides
a simple means for clock control in MINimum mode 80C86
and 80C88 systems. S2/STOP can be used as an indepen-
dent STOP control when S1 and S0 are held in the logical
HIGH state. Keeping the S0 and S1 inputs at a logic 1 level
and transitioning S2/STOP from high to low will meet the
passive 111 state prior to a 011 state requirement of the
82C85. This feature allows 82C85 operation with the 80C86
and 80C88 in the MINimum mode, provides compatibility
with other static CMOS microprocessors and allows maxi-
mum flexibility in a system.
With S2/STOP being used as a stand-alone STOP com-
mand line, system clocks can be controlled via an 82C55A
programmable peripheral interface or other similar interface
circuits. This is accomplished by driving the S2/STOP input
with a PORT pin on the 82C55A (See Figure 1). The
82C55A port pin should be configured as an output and
must present a logic HIGH to the S2/STOP input for at least
one CLK cycle, followed by a LOW state. This will meet the
82C85 status input requirement of 111 followed by a 011.
When a logic 0 is written to a 82C55A port pin, the S2/ STOP
pin is pulled low, stopping the system clocks (CLK, CLK50,
PCLK). In essence, the 82C85 is software controlled via the
82C55A. As with the SLO/FST interface, PORT C is a logical
choice for this job since the individual bit set and reset com-
mands available for this port make control of the S2/STOP
input simple.
A START command issued to the 82C85 will override a
STOP command and the 82C85 will begin normal operation.
The low state of the negative-edge triggered S2/STOP input
will not prohibit the clocks from restarting. After a START or
RES command, the 82C85 must see a passive (111) state
followed by a HALT (011) state to stop the system clocks. To
accomplish this, the 82C55A port output must be brought
high and then returned low again for the 82C85 to recognize
the next STOP command.
External Decode Adds Halt Control
SS0, IO/M and DT/R can identify a MINimum mode 80C88
HALT execution. During T2 of the system timing (while ALE
is high), SS0, IO/M, and DT/R go into a 111 state when the
80C88 is executing a software HALT. These signals cannot
be tied directly to the S2/STOP, S1 and S0 inputs since they
are not guaranteed to go into a passive state prior to their
111 state. These signals can be decoded during the time
ALE is high to indicate a software HALT execution.
Slow Mode
When continuous operation is critical but power consumption
remains a concern, the 82C85 SLOW mode operation pro-
vides a lower frequency at the CLK and CLK50 outputs
(crystal/EFI frequency divided by 768). The frequency of
PCLK is unaffected. The SLOW mode allows the CPU and
the system to operate at a reduced rate which, in turn,
reduces system power.
For example, the operating power for the 80C86 or 80C88
CPU is 10mA/MHz of clock frequency. When the SLOW
mode is used in a typical 5MHz system, CLK and CLK50 run
at approximately 20kHz. At this reduced frequency, the aver-
age operating current of the CPU drops to 200µA. Adding
the 80C86/88 500µA standby current brings the total current
to 700µA.
While the CPU and peripherals run slower and the 82C85
CLK and CLK50 outputs switch at a reduced frequency, the
main 82C85 oscillator is still running at the maximum fre-
quency (determined by the crystal or EFI input frequency.)
Since CMOS power is directly related to operating fre-
quency, 82C85 power supply current will typically be
reduced by 15-20%.
Clock Slow/Fast Operation
The SLO/FST input determines whether the CLK and CLK50
outputs run at full speed (crystal or EFI frequency divided by
3) or at slow speed (crystal or EFI frequency divided by 768)
(See Figure 4). When in the SLOW mode, 82C85 stop-clock
and stop-oscillator functions operate in the same manner as
in the FAST mode.
Internal logic requires that the SLO/FST pin be held low for
at least 195 oscillator or EFI clock pulses before the SLOW
mode command is recognized. This requirement eliminates
unwanted FAST-to-SLOW mode frequency changes which
could be caused by glitches or noise spikes.
To guarantee FAST mode recognition, the SLO/FST pin
must be held high for at least 6 OSC or EFI pulses. The
82C85 will begin FAST mode operation on the next PCLK
4-303

7페이지


구       성 총 20 페이지수
다운로드[ ID82C85.PDF 데이터시트 ]

당사 플랫폼은 키워드, 제품 이름 또는 부품 번호를 사용하여 검색할 수 있는

포괄적인 데이터시트를 제공합니다.


구매 문의
일반 IC 문의 : 샘플 및 소량 구매
-----------------------------------------------------------------------

IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한
광범위한 전력 반도체를 판매합니다.

전력 반도체 전문업체

상호 : 아이지 인터내셔날

사이트 방문 :     [ 홈페이지 ]     [ 블로그 1 ]     [ 블로그 2 ]



관련 데이터시트

부품번호상세설명 및 기능제조사
ID82C82

CMOS Octal Latching Bus Driver

Intersil Corporation
Intersil Corporation
ID82C83H

CMOS Octal Latching Inverting Bus Driver

Intersil Corporation
Intersil Corporation

DataSheet.kr       |      2020   |     연락처      |     링크모음      |      검색     |      사이트맵