Datasheet.kr   

ID82C52 데이터시트 PDF




Intersil Corporation에서 제조한 전자 부품 ID82C52은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

PDF 형식의 ID82C52 자료 제공

부품번호 ID82C52 기능
기능 CMOS Serial Controller Interface
제조업체 Intersil Corporation
로고 Intersil Corporation 로고


ID82C52 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.




전체 19 페이지수

미리보기를 사용할 수 없습니다

ID82C52 데이터시트, 핀배열, 회로
82C52
March 1997
CMOS Serial Controller Interface
Features
• Single Chip UART/BRG
• DC to 16MHz (1M Baud) Operation
• Crystal or External Clock Input
• On-Chip Baud Rate Generator - 72 Selectable Baud
Rates
• Interrupt Mode with Mask Capability
• Microprocessor Bus Oriented Interface
• 80C86 Compatible
• Single +5V Power Supply
• Low Power Operation . . . . . . . . . . . . . . . 1mA/MHz Typ
• Modem Interface
• Line Break Generation and Detection
• Operating Temperature Range:
- C82C52 . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to +70oC
- I82C52 . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC
- M82C52 . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
Description
The Intersil 82C52 is a high performance programmable
Universal Asynchronous Receiver/Transmitter (UART) and
Baud Rate Generator (BRG) on a single chip. Utilizing the
Intersil advanced Scaled SAJI IV CMOS process, the 82C52
will support data rates up to 1M baud asynchronously with a
16X clock (16MHz clock frequency).
The on-chip Baud Rate Generator can be programmed for
any one of 72 different baud rates using a single industry
standard crystal or external frequency source. A unique pre-
scale divide circuit has been designed to provide standard
RS-232-C baud rates when using any one of three industry
standard crystals (1.8432MHz, 2.4576MHz, or 3.072MHz).
A programmable buffered clock output (CO) is available and
can be programmed to provide either a buffered oscillator or
16X baud rate clock for general purpose system usage.
Ordering Information
PACKAGE
PDIP
PLCC
CERDIP
SMD#
CLCC
SMD#
TEMPERATURE
RANGE
0oC to +70oC
-40oC to +85oC
0oC to +70oC
-40oC to +85oC
0oC to +70oC
-40oC to +85oC
-55oC to +125oC
-55oC to +125oC
1M BAUD
CP82C52
IP82C52
CS82C52
IS82C52
CD82C52
ID82C52
MD82C52/B
8501501XA
MR82C52/B
85015013A
PKG. NO.
E28.6
E28.6
N28.45
N28.45
F28.6
F28.6
F28.6
F28.6
J28.A
J28.A
Pinouts
82C52 (PDIP, CERDIP)
TOP VIEW
RD 1
WR 2
D0 3
D1 4
D2 5
D3 6
D4 7
D5 8
D6 9
D7 10
A0 11
A1 12
IX 13
OX 14
28 CSO
27 VCC
26 DR
25 SDI
24 INTR
23 RST
22 TBRE
21 CO
20 RTS
19 DTR
18 DSR
17 CTS
16 GND
15 SDO
82C52 (PLCC, CLCC)
TOP VIEW
4 3 2 1 28 27 26
D2 5
25 SDI
D3 6
24 INTR
D4 7
23 RST
D5 8
D6 9
22 TBRE
21 CO
D7 10
20 RTS
A0 11
19 DTR
12 13 14 15 16 17 18
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
5-1
File Number 2950.1




ID82C52 pdf, 반도체, 판매, 대치품
82C52
Reset
During and after power-up, the 82C52 Reset Input (RST)
must be held high for at least two IX clock cycles in order to
initialize and drive the 82C52 circuits to an idle mode until
proper programming can be done. A high on RST causes
the following events to occur
• Resets the internal Baud Rate Generator (BRG) circuit
clock counters and bit counters. The Baud Rate Select
Register (BRSR) is not affected (except for bit 7 which is
reset to 0).
• Clears the UART Status Register (USR) except for
Transmission Complete (TC) and Transmit Buffer Register
Empty (TBRE) which are set. The Modem Control
Register (MCR) is also cleared. All of the discrete lines,
memory elements and miscellaneous logic associated
with these register bits are also cleared or turned off. Note
that the UART Control Register (UCR) is not affected.
Following removal of the reset condition (RST = low), the
82C52 remains in the idle mode until programmed to its
desired system configuration.
Programming The 82C52
The complete functional definition of the 82C52 is
programmed by the systems software. A set of control words
(UCR, BRSR and MCR) must be sent out by the CPU to
initialize the 82C52 to support the desired communication
format. These control words will program the character
length, number of stop bits, even/odd/no parity, baud rate,
etc. Once programmed, the 82C52 is ready to perform its
communication functions.
The control registers can be written to in any order. However,
the MCR should be written to last because it controls the
interrupt enables, modem control outputs and the receiver
enable bit. Once the 82C52 is programmed and operational,
these registers can be updated any time the 82C52 is not
immediately transmitting or receiving data.
Table 1. Shows the control signals required to access 82C52
internal registers.
UART Control Register (UCR)
The UCR is a write only register which configures the UART
transmitter and receiver circuits. Data bits D7 and D6 are not
used but should always be set to a logic zero (0) in order to
insure software compatibility with future product upgrades.
During the Echo Mode, the transmitter always repeats the
received word and parity, even when the UCR is
programmed with different or no parity. See Figure 1.
TABLE 1.
CS0 A1
00
00
00
00
01
01
01
01
A0 WR RD
OPERATION
0 0 1 Data Bus Transmitter Buffer
Register (TBR)
0 1 0 Receiver Buffer Register
(RBR) Data Bus
1 0 1 Data Bus UART Control
Register (UCR)
1 1 0 UART Status Register
(USR) Data Bus
0 0 1 Data Bus Modem Control
Register (MCR)
0 1 0 MCR Data Bus
1 0 1 Data Bus Bit Rate Select
Register (BRSR)
1 1 0 Modem Status Register
(MSR) Data Bus
D7 D6 D5 D4 D3 D2 D1 D0
Stop Bit
Select
0 = 1 Stop Bits
1 = 1.5 Stop Bits (Tx)
and 1 Stop Bit (Rx)
If 5 Data Bits Selected
1 = 2 Stop Bits for 6, 7
or 8 Data Bits Selected
Parity
Control
000 = Tx and Rx Even
001 = Tx and Rx Odd
010 = Tx Even, Rx
Odd
011 = Tx Odd, Rx
Even
100 = Tx Even, Rx
Check Disabled
101 = Tx Odd, Rx
Check Disabled
11X = Generation and
Check Disabled
Word
Length
Select
00 = 5 Bits
01 = 6 Bits
10 = 7 Bits
11 = 8 Bits
Reserved Set to 00 for Future
Product Upgrade
Compatibility
FIGURE 1. UCR
5-4

4페이지










ID82C52 전자부품, 판매, 대치품
82C52
D7 D6 D5 D4 D3 D2 D1 D0
Parity Error
(PE)
0 = No Error
1 = Error
Framing Error 0 = No Error
(FE)
1 = Error
Overrun Error 0 = No Error
(OE)
1 = Error
Received
0 = No Break
Break (RBRK) 1 = Break
Modem Status
(MS)
0 = No Status
Change
1 = Status
Change
Transmission
Complete
(TC)
0 = Not
Complete
1 = Complete
Transmitter
0 = Not Empty
Buffer Register 1 = Empty
Empty (TBRE)
Data Ready
(DR)
0 = Not Ready
1 = Ready
FIGURE 5. USR
Modem Status Register (MSR)
The MSR allows the CPU to read the modem signal inputs
by accessing the data bus interface of the 82C52. Like all of
the register images of external pins in the 82C52, true logic
levels are represented by a high (1) signal level. By following
this consistent definition, the system software need not be
concerned with whether external signals are high or low true.
In particular, the modem signal inputs are low true, thus a 0
(true assertion) at a modem input pin is represented by a 1
(true) in the MSR.
Any change of state in any modem input signals will set the
Modem Status (MS) bit in the USR register. When this hap-
pens, an interrupt (INTR) will be generated if the MIEN and
INTEN bits of the MCR are enabled.
The Data Set Ready (DSR) input is a status indicator from
the modem to the 82C52 which indicates that the modem is
ready to provide received data to the 82C52 receiver cir-
cuitry.
Clear to Send (CTS) is both a status and control signal from
the modem that tells the 82C52 that the modem is ready to
receive transmit data from the 82C52 transmitter output
(SDO). A high (false) level on this input will inhibit the 82C52
from beginning transmission and if asserted in the middle of
a transmission will only permit the 82C52 to finish transmis-
sion of the current character.
D7 D6 D5 D4 D3 D2 D1 D0
Clear to Send
(CTS)
Data Set
Ready (DSR)
0
0
Undefined
0 = False
1 = Truer
0 = False
1 = True
FIGURE 6. MSR
Receiver Buffer Register (RBR)
The receiver circuitry in the 82C52 is programmable for 5, 6,
7 or 8 data bits per character. For words of less than 8 bits,
the data is right justified to the Least Significant Bit (LSB =
D0). Bit D0 of a data word is always the first data bit
received. The unused bits in a less than 8-bit word, at the
parallel interface, are set to a logic zero (0) by the 82C52.
Received data at the SDI input pin is shifted into the
Receiver Register by an internal 1x clock which has been
synchronized to the incoming data based on the position of
the start bit. When a complete character has been shifted
into the Receiver Register, the assembled data bits are par-
allel loaded into the Receiver Buffer Register. Both the DR
output pin and DR flag in the USR register are set. This dou-
ble buffering of the received data permits continuous recep-
tion of data without losing any of the received data.
While the Receiver Register is shifting a new character into
the 82C52, the Receiver Buffer Register is holding a previ-
ously received character for the system CPU to read. Failure
to read the data in the RBR before complete reception of the
next character can result in the loss of the data in the
Receiver Register. The OE flag in the USR register indicates
the overrun condition.
D7 D6 D5 D4 D3 D2 D1 D0
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
5-Bit
Word
6-Bit
Word
7-Bit
Word
8-Bit
Word
FIGURE 7. RBR
Transmitter Buffer Register (TBR)
The Transmitter Buffer Register (TBR) accepts parallel data
from the data bus (D0-D7) and holds it until the Transmitter
Register is empty and ready to accept a new character for
transmission. The transmitter always has the same word
length and number of stop bits as the receiver. For words of
less than 8 bits the unused bits at the microprocessor data
bus are ignored by the transmitter.
D7 D6 D5 D4 D3 D2 D1 D0
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
5-Bit
Word
6-Bit
Word
7-Bit
Word
8-Bit
Word
FIGURE 8. TBR
5-7

7페이지


구       성 총 19 페이지수
다운로드[ ID82C52.PDF 데이터시트 ]

당사 플랫폼은 키워드, 제품 이름 또는 부품 번호를 사용하여 검색할 수 있는

포괄적인 데이터시트를 제공합니다.


구매 문의
일반 IC 문의 : 샘플 및 소량 구매
-----------------------------------------------------------------------

IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한
광범위한 전력 반도체를 판매합니다.

전력 반도체 전문업체

상호 : 아이지 인터내셔날

사이트 방문 :     [ 홈페이지 ]     [ 블로그 1 ]     [ 블로그 2 ]



관련 데이터시트

부품번호상세설명 및 기능제조사
ID82C50A

CMOS Asynchronous Communications Element

Intersil Corporation
Intersil Corporation
ID82C52

CMOS Serial Controller Interface

Intersil Corporation
Intersil Corporation

DataSheet.kr       |      2020   |     연락처      |     링크모음      |      검색     |      사이트맵