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C9531 데이터시트 PDF




Cypress Semiconductor에서 제조한 전자 부품 C9531은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

PDF 형식의 C9531 자료 제공

부품번호 C9531 기능
기능 PCIX I/O System Clock Generator with EMI Control Features
제조업체 Cypress Semiconductor
로고 Cypress Semiconductor 로고


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C9531 데이터시트, 핀배열, 회로
C9531
PCIX I/O System Clock Generator with EMI Control Features
Features
• Dedicated clock buffer power pins for reduced noise,
crosstalk and jitter
• Input clock frequency of 25 MHz to 33 MHz
• Output frequencies of XINx1, XINx2, XINx3 and XINx4
• One output bank of 5 clocks.
• One REF XIN clock output.
• SMBus clock control interface for individual clock
disabling and SSCG control
• Output clock duty cycle is 50% (± 5%)
• < 250 ps skew between output clocks within a bank
• Output jitter <175 ps
• Spread Spectrum feature for reduced electromagnetic
interference (EMI)
• OE pin for entire output bank enable control and
testability
• 28-pin SSOP and TSSOP packages
Block Diagram
Table 1. Test Mode Logic Table[1]
OE
HIGH
HIGH
HIGH
HIGH
LOW
Input Pins
S1
LOW
LOW
HIGH
HIGH
X
S0
LOW
HIGH
LOW
HIGH
X
Output Pins
CLK
REF
XIN XIN
2 * XIN
XIN
3 * XIN
XIN
4 * XIN
XIN
Three-state Three-state
Pin Configuration
SSCG#
SSCG
Logic
XIN
XOUT
/N 1
0
SDATA
SCLK
IA(0:2)
S(0,1)
I2C
Control
Logic
CLK0
CLK1
CLK2
CLK3
CLK4
OE
GOOD#
REF
Note:
1. XIN is the frequency of the clock on the device’s XIN pin.
REF
VDD
XIN
XOUT
VSS
S0
S1
GOOD#
VSS
IA0
IA1
IA2
VDDA
OE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 SDATA
27 SCLK
26 VSS
25 VDDP
24 CLK0
23 CLK1
22 CLK2
21 VSS
20 VDDP
19 CLK3
18 CLK4
17 VDDA
16 VSS
15 SSCG#
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07034 Rev. *D
Revised May 12, 2003




C9531 pdf, 반도체, 판매, 대치품
C9531
Byte 0: Output Register (continued)
20
10
0 1 HWSEL
Not used
Not used
Hardware/SMBus frequency control. 1 = Hardware (pins 6, 7, and 15), 0 = SMBus
Byte 0 bits 3, 4, & 6
Table 4. Clarification Table for Byte0, bit 5
Byte0, bit6
0
0
Byte0, bit5
0
1
Description
Frequency generated from second PLL
Frequency generated from XIN
1 0 Spread @ –1.0%
1 1 Spread @ –0.5%
Table 5. Test Table
Test Function Clock
Frequency
CLK
XIN/4
Outputs
REF
XIN
Note
XIN is the frequency of the clock that is present on the
XIN input during test mode.
Byte 1: CPU Register
Bit @Pup
71
61
51
41
31
21
11
01
Name
REFEN
Reserved
Reserved
REF Output Enable
0 = Disable, 1= Enable
Reserved
Reserved
Reserved
Reserved
Reserved
Description
Byte 2: PCI Register
Bit @Pup
71
61
51
41
31
21
11
01
Name
18
19
22
23
24
Reserved
Reserved
Reserved
CLK4 Output Enable
0 = Disable, 1= Enable
CLK3 Output Enable
0 = Disable, 1= Enable
CLK2Output Enable
0 = Disable, 1= Enable
CLK1 Output Enable
0 = Disable, 1= Enable
CLK0 Output Enable
0 = Disable, 1= Enable
Description
Document #: 38-07034 Rev. *D
Page 4 of 10

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C9531 전자부품, 판매, 대치품
C9531
Absolute Maximum Conditions
Parameter
Description
Condition
Min.
Max.
Unit
VDD,VDDP
VDDA
VIN
TS
TA
TJ
ESDHBM
ØJC
ØJA
UL–94
Core Supply Voltage
Analog Supply Voltage
Input Voltage
Temperature, Storage
Temperature, Operating Ambient
Temperature, Junction
ESD Protection (Human Body Model)
Dissipation, Junction to Case
Dissipation, Junction to Ambient
Flammability Rating
Relative to V SS
Non Functional
Functional
Functional
MIL-STD-883, Method 3015
Mil-Spec 883E Method 1012.1
JEDEC (JESD 51)
At 1/8 in.
–0.5
–0.5
–0.5
–65
0
2000
4.6
4.6
VDD + 0.5
+150
70
150
V–0
V
V
VDC
°C
°C
°C
V
°C/W
°C/W
MSL
Moisture Sensitivity Level
1
Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing
is NOT required.
DC Electrical Specifications
Parameter
Description
VDD, VDDP,
VDDA
VILI2C
VIHI2C
VIL
VIH
IIL
3.3V Operating Voltage
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Input Leakage Current
VOL
VOH
IOZ
CIN
COUT
LIN
CXTAL
Output Low Voltage
Output High Voltage
High-Impedance Output Current
Input Pin Capacitance
Output Pin Capacitance
Pin Inductance
Crystal Pin Capacitance
VXIH
VXIL
IDD
Xin High Voltage
Xin Low Voltage
Dynamic Supply Current
IPD Power-down Supply Current
AC Electrical Specifications
Parameter
Crystal
TDC
Description
XIN Duty Cycle
XINFREQ
TR / TF
XIN Frequency
XIN Rise and Fall Times
Condition
3.3V ± 5%
SDATA, SCLK
SDATA, SCLK
except Pull-ups or Pull-downs
0 < VIN < VDD
IOL = 1 mA
IOH = –1 mA
From XIN and XOUT pins to
ground
At 133 MHz and all outputs
loaded per Table 7
PD# Asserted
Min.
3.135
Max.
3.465
2.2
VSS–0.5
2.0
–5
1
0.8
VDD+0. 5
5
– 0.4
2.4 –
–10 10
25
36
–7
32 38
0.7VDD
0
VDD
0.3VDD
300
–1
Unit
V
V
V
V
µA
V
V
µA
pF
pF
nH
pF
V
V
mA
mA
Condition
Min. Max. Unit
The device will operate reliably with input duty
cycles up to 30/70%
When Xin is driven from an external clock source
Measured between 0.3VDD and 0.7VDD
45 55 %
25 33.3 MHz
– 10.0 ns
Document #: 38-07034 Rev. *D
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