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PDF DS1023 Data sheet ( Hoja de datos )
| Número de pieza | DS1023 | |
| Descripción | 8-Bit Programmable Timing Element | |
| Fabricantes | Dallas Semiconducotr | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de DS1023 (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
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DS1023
8-Bit Programmable Timing Element
www.dalsemi.com
FEATURES
Step sizes of 0.25 ns, 0.5 ns, 1 ns, 2 ns, 5 ns
On-chip reference delay
Configurable as delay line, pulse width
modulator, or free-running oscillator
Can delay clocks by a full period or more
Guaranteed monotonicity
Parallel or serial programming
Single 5V supply
16-pin DIP or SOIC package
PIN ASSIGNMENT
IN
LE
Q/P0
CLK/P1
D/P2
P3
P4
GND
1
2
3
4
5
6
7
8
16 VCC
15 OUT/OUT
14 P/S
13 P7
12 P6
11 MS
10 P5
9 REF/PWM
DS1023 300-mil DIP
DS1023S 300-mil SOIC
PIN DESCRIPTION
IN - Input
P0/Q
- Parallel Input P0 (parallel mode)
- Serial Data Output (serial mode)
P1/CLK
- Parallel Input P1 (parallel mode)
- Serial Input Clock (serial mode)
P2/D
- Parallel Input P2 (parallel mode)
- Serial Data Input (serial mode)
P3 - P7
- Remaining Parallel Inputs
GND
- Ground
OUT/ OUT - Output
REF/PWM - Reference or PWM Output
P /S - Parallel / Serial Programming
Select
MS - Output Mode Select
LE - Input Latch Enable
VCC - Supply Voltage
DESCRIPTION
The DS1023 is an 8-bit programmable delay line similar in function to the DS1020/DS1021.
Additional features have been added to extend the range of applications:
The internal delay line architecture has been revised to allow clock signals to be delayed by up to a full
period or more. Combined with an on-chip reference delay (to offset the inherent or “step zero” delay of
the device) clock phase can now be varied over the full 0-360 degree range.
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022300
1 page  
MS = 1 Figure 4
DS1023
Output Function
Pulse Width Modulated Output
Delayed and Inverted Output
Name
PWM
OUT
Pin Number
9
15
PWM is an output triggered by the rising edge of the input waveform. After a time interval approximately
equal to the Step Zero delay of the device the PWM output will go high. The output will return to a low
level after a time interval determined by the programmed values (Table 1). Hence output pulse widths can
be obtained from (nearly) zero to the full delay range of the device. In practice the minimum output pulse
width is limited by the response time of the device to approximately 5ns. Programmed values less than
this will result in degradation of the output high level voltage until ultimately no discernible output pulse
is produced. The frequency/repetition rate of the output is determined by the input frequency. The input
pulse width can be shorter than the output pulse width, and is limited only by the minimum input pulse
width specification. The PWM function is not “re-triggerable”, subsequent input trigger pulses should
not be present until the output has returned to a low level.
OUT is an inverted copy of the input waveform that is delayed by an amount set by the programmed
values (Table 1). A programmed value of zero will still result in a non-zero delay as indicated in the Step
Zero delay specification. The OUT pin may also be externally connected to the input pin to produce a
free-running oscillator. The frequency of oscillation is determined by the programmed delay value of the
device (see Table 2).
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5 Page 
AC ELECTRICAL CHARACTERISTICS –
DS1023-050 Delay Specifications
PARAMETER
SYMBOL MIN
Step Zero Delay
-absolute
-wrt REF
Reference Delay
Delay Step Size
Maximum Delay
tD0
tDREF0
tREF
tSTEP
-2
0
-absolute
-wrt REF
Delay Matching, Rising Edge
to Falling Edge
tDMAX
tDREF
139
123
-1
Integral Non-linearity
(deviation from straight line)
OUT Delta Delay
terr
tINV0
-2
0
IN High to PWM High
Minimum PWM Output
tPWM0
Pulse Width
Minimum Input Pulse Width
Minimum Input Period
tPWM
tWI
5
20
40
Input Rise and Fall Times
tr, tf
0
AC ELECTRICAL CHARACTERISTICS –
DS1023-100 Delay Specifications
PARAMETER
SYMBOL MIN
Step Zero Delay
-absolute
-wrt REF
Reference Delay
Delay Step Size
Maximum Delay
tD0
tDREF0
tREF
tSTEP
-2
0
-absolute
-wrt REF
Delay Matching, Rising Edge
tDMAX
tDREF
262
247
-1
to Falling Edge
Integral Non-linearity
(deviation from straight line)
terr
-4
OUT Delta Delay
tINV0
0
IN High to PWM High
Minimum PWM Output
tPWM0
Pulse Width
Minimum Input Pulse Width
Minimum Input Period
tPWM
tWI
5
20
40
Input Rise and Fall Times
tr, tf
0
DS1023
(TA= 0°C to 70°C; VCC = 5V ±=5%)
TYP MAX UNITS NOTES
16.5 22
-1.5 0
18 22
0.5 1.5
ns 1, 13
ns 2, 14
ns 3, 13
ns 4
144
127.5
154
132
+1
ns 5, 13
ns 6, 14
ns 15
0 +2
12
16.5 22
1
ns 7
ns 8
ns 9, 13
ns 10
ns 11
ns 12
µs 16
(TA = 0°C – 70°C; VCC = 5V ±=5%)
TYP
MAX UNITS NOTES
16.5 22
-1.5 0
18 22
1 1.5
ns 1, 13
ns 2, 14
ns 3, 13
ns 4
272 285 ns 5, 13
255 263 ns 6, 14
+1 ns 15
0 +4 ns 7
12
16.5 22
ns 8
ns 9, 13
ns 10
ns 11
ns 12
1 µs 16
11 of 16
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet DS1023.PDF ] | |
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