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ST24E64 데이터시트 PDF




ST Microelectronics에서 제조한 전자 부품 ST24E64은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

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부품번호 ST24E64 기능
기능 (ST24E64 / ST25E64) SERIAL EXTENDED ADDRESSING COMPATIBLE WITH I2C BUS 64K (8K x 8) EEPROM
제조업체 ST Microelectronics
로고 ST Microelectronics 로고


ST24E64 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.




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ST24E64 데이터시트, 핀배열, 회로
ST24E64
ST25E64
SERIAL EXTENDED ADDRESSING COMPATIBLE
WITH I2C BUS 64K (8K x 8) EEPROM
COMPATIBLE with I2C EXTENDED
ADDRESSING
TWO WIRE SERIAL INTERFACE,
SUPPORTS 400kHz PROTOCOL
1 MILLION ERASE/WRITE CYCLES, OVER
the FULL SUPPLY VOLTAGE RANGE
40 YEARS DATA RETENTION
SINGLE SUPPLY VOLTAGE
– 4.5V to 5.5V for ST24E64 version
– 2.5V to 5.5V for ST25E64 version
WRITE CONTROL FEATURE
BYTE and PAGE WRITE (up to 32 BYTES)
BYTE, RANDOM and SEQUENTIAL READ
MODES
SELF TIMED PROGRAMING CYCLE
AUTOMATIC ADDRESS INCREMENTING
ENHANCED ESD/LATCH UP
PERFORMANCES
PRELIMINARY DATA
8
1
PSDIP8 (B)
0.25mm Frame
8
1
SO8 (M)
200mil Width
Figure 1. Logic Diagram
DESCRIPTION
The ST24/25E64 are 64K bit electrically erasable
programmable memories (EEPROM), organized
as 8 blocks of 1024 x 8 bits. The ST25E64 operates
with a power supply value as low as 2.5V. Both
Plastic Dual-in-Line and Plastic Small Outline pack-
ages are available.
Table 1. Signal Names
E0 - E2
SDA
SCL
WC
VCC
VSS
Chip Enable Inputs
Serial Data Address Input/Output
Serial Clock
Write Control
Supply Voltage
Ground
VCC
3
E0-E2
SCL
WC
ST24E64
ST25E64
SDA
VSS
AI01204B
November 1996
This is preliminary information on a new product now in development or undergoing evaluatio n.Details are subject to change without notice.
1/16




ST24E64 pdf, 반도체, 판매, 대치품
ST24E64, ST25E64
Figure 3. Maximum RL Value versus Bus Capacitance (CBUS) for an I2C Bus, fC = 400kHz
20
VCC
16
12
8
4
VCC = 5V
SDA
MASTER SCL
RL RL
CBUS
CBUS
0
25 50 75 100
CBUS (pF)
AI01115
DEVICE OPERATION
I2C Bus Background
The ST24/25E64support the extended addressing
I2C protocol. This protocol defines any device that
sends data onto the bus as a transmitter and any
device that reads the data as a receiver. The device
that controls the data transfer is known as the
master and the other as the slave. The master will
always initiate a data transfer and will provide the
serial clock for synchronisation. The ST24/25E64
are always slave devices in all communications.
Start Condition. START is identified by a high to
low transition of the SDA line while the clock SCL
is stable in the high state. A START condition must
precede any command for data transfer. Except
during a programming cycle, the ST24/25E64 con-
tinuously monitor the SDA and SCL signals for a
START condition and will not respond unless one
is given.
Stop Condition. STOPis identified by a low to high
transition of the SDA line while the clock SCL is
stable in the high state. A STOP condition termi-
nates communication between the ST24/25E64
and the bus master. A STOP condition at the end
of a Read command forces the standby state. A
STOP condition at the end of a Write command
triggers the internal EEPROM write cycle.
Acknowledge Bit (ACK). An acknowledge signal
is used to indicate a successful data transfer. The
bus transmitter, either master or slave, will release
the SDA bus after sending 8 bits of data. During the
9th clock pulse the receiver pulls the SDA bus low
to acknowledge the receipt of the 8 bits of data.
Data Input. During data input the ST24/25E64
sample the SDA bus signal on the rising edge of
the clock SCL. For correct device operation the
SDA signal must be stable during the clock low to
high transition and the data must change ONLY
when the SCL line is low.
Device Selection. To start communication be-
tween the bus master and the slave ST24/25E64,
the master must initiate a START condition. The 8
bits sent after a START condition are made up of a
device select of 4 bits that identifies the device type,
3 Chip Enable bits and one bit for a READ (RW =
1) or WRITE (RW = 0) operation. There are two
modes both for read and write. These are summa-
rised in Table 4 and described hereafter. A commu-
nication between the master and the slave is ended
with a STOP condition.
4/16

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ST24E64 전자부품, 판매, 대치품
Figure 5. AC Waveforms
ST24E64, ST25E64
SCL
SDA IN
tCHCL
tCLCH
tDLCL
tDXCX
tCHDX
START
CONDITION
tCLDX
SDA
SDA
INPUT CHANGE
tCHDH
tDHDL
STOP &
BUS FREE
SCL
SDA OUT
tCLQV
DATA VALID
tCLQX
DATA OUTPUT
SCL
SDA IN
tDHDL
tCHDH
STOP
CONDITION
tW
WRITE CYCLE
tCHDX
START
CONDITION
AI00795
7/16

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ST24E64

(ST24E64 / ST25E64) SERIAL EXTENDED ADDRESSING COMPATIBLE WITH I2C BUS 64K (8K x 8) EEPROM

ST Microelectronics
ST Microelectronics

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