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PDF SX21V001-Z4 Data sheet ( Hoja de datos )
| Número de pieza | SX21V001-Z4 | |
| Descripción | CUSTOMERS ACCEPTANCE SPECIFICATIONS SX21V001-Z4A | |
| Fabricantes | Hitachi Semiconductor | |
| Logotipo |  |
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Displays, Hitachi, Ltd.
3300 Hayano, Mobara City
Chiba Pref. 297 Japan
TEL : +81-475-25-9005 (Dial In)
FAX : +81-475-22-5217
For Messrs :
Date : Nov. 4, '99
CUSTOMER'S ACCEPTANCE SPECIFICATIONS
SX21V001-Z4
CONTENTS
No. ITEM
1 COVER
2 RECORD OF REVISION
3 MECHANICAL DATA
4 ABSOLUTE MAXIMUM RATINGS
5 ELECTRICAL CHARACTERISTICS
6 OPTICAL CHARACTERISTICS
7 BLOCK DIAGRAM
8 INTERFACE TIMING CHART
9 DIMENSIONAL OUTLINE
10 APPEARANCE STANDARD
11 PRECAUTION IN DESIGN
12 DESIGNATION OF LOT MARK
13 PRECAUTION FOR USE
Sheet No.
3284PS 2701 - SX21V001-Z4 - 4
3284PS 2702 - SX21V001-Z4 - 4
3284PS 2703 - SX21V001-Z4 - 4
3284PS 2704 - SX21V001-Z4 - 4
3284PS 2705 - SX21V001-Z4 - 4
3284PS 2706 - SX21V001-Z4 - 4
3284PS 2707 - SX21V001-Z4 - 4
3284PS 2708 - SX21V001-Z4 - 4
3283PS 2709 - SX21V001-Z4 - 4
3284PS 2710 - SX21V001-Z4 - 4
3284PS 2711 - SX21V001-Z4 - 4
3284PS 2712 - SX21V001-Z4 - 4
3284PS 2713 - SX21V001-Z4 - 4
Page
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Accepted by :
Displays, Hitachi, Ltd.
Sh.
No.
Proposed by :
3284PS 2701 - SX21V001-Z4 - 4
Page 1-1/1
1 page  
5. ELECTRICAL CHARACTERISTICS
5. 1 ELECTRICAL CHARACTERISTICS OF LCD
ITEM
SYMBOL
CONDITION
VSS=0V
MIN
TYP
MAX UNIT
Pow er Supply Voltage
VDD
VDD-VSS=3.3V 3.15
3.30
3.45 V
Contrast Adjustment
Voltage
(Note 1)
VCON
-
0.8 - 2.8 V
Input Voltage for Logic
Circuits
(Note 2)
Vi
"H" level
"L" level
0.8VDD
0
-
-
VDD
0.2VDD
V
Pow er Supply Current
(Note 3)(Note 4)
IDD
VDD-VSS=3.3V
-
60 72 mA
Input Leak Current
Icon(Note5) Vcon=0.8∼2.8V
Iin (Note2) Vin=VDDorVSS
-
-
- (20)
µA
- ±1.0
Contrast Adjustment
Voltage
(Note 6)
Vcon
Frame Frequency
(Note 7)
f FLM
Ta= 5°C, φ=0°
Ta=25°C, φ=0°
Ta=40°C, φ=0°
-
0.8
-
-
100
(1.2)
(1.8)
(2.4)
120
-
-V
2.8
150 Hz
(Note 1) In proportion as the VCON voltage decrease the brightness w ill increase.
(Note 2) DISP OFF, FLM, CL1, CL2, UD0∼UD7, LD0∼LD7
(Note 3) fFLM=120Hz, Ta=25°C, Display pattern:Checker pattern.
(Note 4) Rush Current of Pow er ON : 2A(PK) × 100µs
(Note 5) VCON
(Note 6) The Contrast Adjustment Voltage is specified as 1.8±0.3V under the condition, w hen an
optimum contrast is obtained by naked eyes as the "Q" test pattern.
fFLM=120Hz, 1/240Duty
(Note 7) Need to make sure of flickering and rippling of display w hen setting the Frame Frequency
in your set.
(Note 8) Absolute maximum ratings voltage of CFL cable for this module is as follow s.
VCFL side : 2kV
VSS side : 300V
This inverter design shall not exceed the rated voltage.
Displays, Date Nov. 4, '99 Sh. 3284PS 2705 - SX21V001-Z4 - 4
Hitachi, Ltd.
No.
Page 5-1/2
5 Page 
8. INTERFACE TIMING CHART
8.1 TIMING CHART
CL1
CL2
Dummy data
UD7
RB
Y1 Y9
UD6
GR
Y2 Y10
UD1
RB
Y7 Y15
UD0
Dummy data
GR
Y8 Y16
LD7
LD6
LD1
LD0
RB
Y1921 Y1929
GR
Y1922 Y1930
RB
Y1927 Y1935
GR
Y1928 Y1936
X1
X241
FLM
(Reduction)
CL1
FLM
(240+n) × T
G
Y1913
B
Y1914
G
Y1919
B
Y1920
G
Y1913
B
Y1914
G
Y1919
B
Y1920
X2
X242
Note(1)
UD0~UD7
X1 X2
Y239 Y240 Dummy data
LD0~LD7
X241 X242
Y479 Y480 Dummy data
Note(1) : The interval of CL1 pulse must be same including the vertical blanking period.
Dis p l a ys ,
Hitachi, Ltd. Date
Nov. 4, '99
Sh. 3284PS 2708 - SX21V001-Z4 - 4
No.
Page 8-1/7
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SX21V001-Z4.PDF ] | |
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