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PDF SY100ELT25 Data sheet ( Hoja de datos )
| Número de pieza | SY100ELT25 | |
| Descripción | DIFFERENTIAL ECL-to-TTL TRANSLATOR | |
| Fabricantes | Micrel Semiconductor | |
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DIFFERENTIAL
ECL-to-TTL
TRANSLATOR
SY100ELT25
FEATURES
s 2.6ns typical propagation delay
s Differential ECL inputs
s 24mA TTL outputs
s Flow-through pinouts
s Available in 8-pin SOIC package
DESCRIPTION
The SY100ELT25 is a differential ECL-to-TTL
translator. Because ECL levels are used, a +5V, –5.2V
(or –4.5V) and ground are required. The small outline 8-
lead SOIC package and the single gate of the ELT25
makes it ideal for those applications where performance,
space and low power are at a premium.
The VBB output allows the ELT25 to also be used in a
single-ended input mode. In this mode the VBB output is
tied to the D input for a non-inverting buffer or the D
input for an inverting buffer. If used the VBB pin should
be bypassed to ground via a 0.01µF capacitor.
PIN CONFIGURATION/BLOCK DIAGRAM
VEE 1
D2
D3
VBB 4
8 VCC
7Q
6 NC
5 GND
SOIC
TOP VIEW
PIN NAMES
Pin
Q
D
VCC
VEE
VBB
GND
Function
TTL Output
Differential ECL Inputs
Positive Supply
Negative Supply
Reference Output
Ground
Rev.: A Amendment: /0
1 Issue Date: October 1999
1 page  
Micrel
8 LEAD SOIC .150" WIDE (Z8-1)
SY100ELT25
Rev. 03
MICREL-SYNERGY 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA
TEL + 1 (408) 980-9191 FAX + 1 (408) 914-7878 WEB http://www.micrel.com
This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or
other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc.
© 2000 Micrel Incorporated
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5 Page | ||
| Páginas | Total 5 Páginas | |
| PDF Descargar | [ Datasheet SY100ELT25.PDF ] | |
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