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PDF SY100EL51 Data sheet ( Hoja de datos )
| Número de pieza | SY100EL51 | |
| Descripción | DIFFERENTIAL CLOCK D FLIP-FLOP | |
| Fabricantes | Micrel Semiconductor | |
| Logotipo |  |
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DIFFERENTIAL
CLOCK D FLIP-FLOP
SY10EL51
SY100EL51
FEATURES
s 475ps propagation delay
s 2.8GHz toggle frequency
s Internal 75KΩ input pull-down resistors
s Available in 8-pin SOIC package
PIN CONFIGURATION/BLOCK DIAGRAM
R1
D2
CLK 3
CLK 4
R
D
Flip-Flop
8 VCC
7Q
6Q
5 VEE
DESCRIPTION
The SY10/100EL51 are differential clock D flip-flops
with reset. These devices are functionally similar to the
E151 devices, with higher performance capabilities. With
propagation delays and output transition times
significantly faster than the E151, the EL51 is ideally
suited for those applications which require the ultimate
in AC performance.
The reset input is an asynchronous, level triggered
signal. Data enters the master portion of the flip-flop
when the clock is LOW and is transferred to the slave,
and thus the outputs, upon a positive transition of the
clock. The differential clock inputs of the EL51 allow the
device to be used as a negative edge triggered flip-flop.
The differential input employs clamp circuitry to
maintain stability under open input (pulled down to VEE)
conditions.
PIN NAMES
Pin
R
D
CLK
Q
SOIC
TOP VIEW
Function
Reset Input
Data Input
Clock Input
Data Output
TRUTH TABLE(1)
DR
LL
HL
XH
NOTE:
1. Z = LOW-to-HIGH transition.
CLK
Z
Z
X
Q
L
H
L
Rev.: E Amendment: /0
1 Issue Date: August, 1998
1 page | ||
| Páginas | Total 4 Páginas | |
| PDF Descargar | [ Datasheet SY100EL51.PDF ] | |
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