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GM71C4400CL 데이터시트 PDF




Hynix Semiconductor에서 제조한 전자 부품 GM71C4400CL은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 GM71C4400CL 자료 제공

부품번호 GM71C4400CL 기능
기능 1M x 4 Bit CMOS DRAM
제조업체 Hynix Semiconductor
로고 Hynix Semiconductor 로고


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GM71C4400CL 데이터시트, 핀배열, 회로
LG Semicon Co.,Ltd.
GM71C(S)4400C/CL
1,048,576 WORDS x 4BIT
CMOS DYNAMIC RAM
Description
Features
The GM71C(S)4400C/CL is the new generation
dynamic RAM organized 1,048,576 words x 4 bit.
GM71C(S)4400C/CL has realized higher density,
higher performance and various functions by
utilizing advanced CMOS process technology. The
GM71C(S)4400C/CL offers Fast Page Mode as a
high speed access Mode. Multiplexed address
inputs permit the GM71C(S)4400C/CL to be
packaged in a standard 300mil 20(26) pin plastic
SOJ and standard 300mil 20(26) pin plastic
TSOP II. The package size provides high system
bit densities and is compatible with widely
available automated testing and insertion
equipment. System oriented features include single
power supply of 5V+/-10% tolerance, direct
interfacing capability with high performance logic
families such as Schottky TTL.
Pin Configuration
20 (26) SOJ
* 1,048,576 Words x 4 Bit Organization
* Fast Page Mode Capability
* Single Power Supply (5V+/-10%)
* Fast Access Time & Cycle Time
(Unit: ns)
tRAC tCAC tRC
tPC
GM71C(S)4400C/CL-60 60 15 110 40
GM71C(S)4400C/CL-70 70 20 130 45
GM71C(S)4400C/CL-80 80 20 150 50
* Low Power
Active : 605/550/495mW (MAX)
Standby : 5.5mW (CMOS level : MAX)
1.1mW (L-version)
* RAS Only Refresh, CAS before RAS Refresh,
Hidden Refresh Capability
* All inputs and outputs TTL Compatible
* 1024 Refresh Cycles/16ms
* 1024 Refresh Cycles/128ms (L-version)
* Battery Back Up Operation (L-version)
20 (26) TSOP II
I/O1
I/O2
WE
RAS
A9
A0 6
A1 7
A2 8
A3 9
VCC 10
VSS
I/O4
I/O3
CAS
OE
15 A8
14 A7
13 A6
12 A5
11 A4
(Top View)
I/O1 1
I/O2 2
WE 3
RAS 4
A9 5
20 VSS
19 I/O4
18 I/O3
17 CAS
16 OE
VSS 20
I/O4 19
I/O3 18
CAS 17
OE 16
1 I/O1
2 I/O2
3 WE
4 RAS
5 A9
A0 6
A1 7
A2 8
A3 9
VCC 10
15 A8
14 A7
13 A6
12 A5
11 A4
A8 15
A7 14
A6 13
A5 12
A4 11
6 A0
7 A1
8 A2
9 A3
10 VCC
NORMAL TYPE
REVERSE TYPE
(Top View)
1




GM71C4400CL pdf, 반도체, 판매, 대치품
LG Semicon
GM71C(S)4400C/CL
Capacitance (VCC = 5V+/-10%, TA = 25C)
Symbol
Parameter
Min Max Unit
CI1 Input Capacitance (Address)
- 5 §Ü
CI2 Input Capacitance (Clocks)
- 7 §Ü
CI/O Data Input, Output Capacitance (Data-In, Out) - 10 §Ü
Note: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. CAS = VIH to disable DOUT.
AC Characteristics (VCC = 5V+/-10%, TA = 0 ~ 70C, Notes 1, 14, 15, 16)
Note
1
1
1, 2
Test Conditions
Input rise and fall times: 5ns
Output load : 2 TTL gate + CL (100§Ü)
Input, output timing reference levels: 0.8V, 2.4V
(Including scope and jig)
Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters)
Symbol
Parameter
GM71C(S)4400 GM71C(S)4400 GM71C(S)4400
C/CL-60
C/CL-70
C/CL-80
Unit
Min Max Min Max Min Max
Note
tRC Random Read or Write Cycle Time
110 - 130 - 150 - ns
tRP RAS Precharge Time
40 - 50 - 60 - ns
tRAS RAS Pulse Width
60 10,000 70 10,000 80 10,000 ns
tCAS CAS Pulse Width
15 10,000 20 10,000 20 10,000 ns
tASR Row Address Set-up Time
0-
0-
0 - ns
tRAH Row Address Hold Time
10 - 10 - 10 - ns
tASC Column Address Set-up Time
0-
0-
0 - ns
tCAH Column Address Hold Time
15 - 15 - 15 - ns
tRCD RAS to CAS Delay Time
20 45 20 50 20 60 ns
8
tRAD RAS to Column Address Delay Time
15 30 15 35 15 40 ns
9
tRSH RAS Hold Time
15 - 20 - 20 - ns
tCSH CAS Hold Time
60 - 70 - 80 - ns
tCRP CAS to RAS Precharge Time
10 - 10 - 10 - ns
tODD OE to DIN Delay Time
15 - 20 - 20 - ns
tDZO OE Delay Time from DIN
0-
0-
0 - ns
tDZC CAS Set-up Time from DIN
0-
0-
0 - ns
tT Transition Time
(Rise and Fall)
3 50 3 50 3 50 ns
7
tREF Refresh Period
- 16 - 16 - 16 ms
Refresh Period (L-version)
- 128 - 128 - 128 ms
4

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GM71C4400CL 전자부품, 판매, 대치품
LG Semicon
Test Mode Cycle
Symbol
Parameter
tWS Test Mode WE Setup Time
tWH Test Mode WE Hold Time
Counter Test Cycle
Symbol
Parameter
tCPT CAS Precharge Time in Counter Test
Cycle
GM71C(S)4400C/CL
GM71C(S)4400 GM71C(S)4400 GM71C(S)4400
C/CL-60
C/CL-70
C/CL-80
Unit
Min Max Min Max Min Max
Note
0 - 0 - 0 - ns
10 - 10 - 10 - ns
GM71C(S)4400 GM71C(S)4400 GM71C(S)4400
C/CL-60
C/CL-70
C/CL-80
Unit
Min Max Min Max Min Max
Note
40 - 40 - 40 - ns
Notes:
1. AC Measurements assume tT = 5ns.
2. Assumes that tRCD<=tRCD(max) and tRAD<=tRAD(max). If tRCD or tRAD is greater than the maximum
recommended value shown in this table, tRAC exceeds the value shown.
3. Measured with a load circuit equivalent to 2TTL loads and 100§Ü.
4. Assumes that tRCD>=tRCD(max) and tRAD<=tRAD(max).
5. Assumes that tRCD<=tRCD(max) and tRAD>=tRAD(max).
6. tOFF(max) defines the time at which the output achieves the open circuit condition and is not
referenced to output voltage levels.
7. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Also,
transition times are measured between VIH and VIL.
8. Operation with the tRCD(max) limit insures that tRAC(max) can be met, tRCD(max) is specified as a
reference point only; if tRCD is greater than the specified tRCD(max) limit, then access time is
controlled exclusively by tCAC.
9. Operation with the tRAD(max) limit insures that tRAC(max) can be met, tRAD(max) is specified as a
reference point only; if tRAD is greater than the specified tRAD(max) limit, then access time is
controlled exclusively by tAA.
7

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관련 데이터시트

부품번호상세설명 및 기능제조사
GM71C4400C

1M x 4 Bit CMOS DRAM

Hynix Semiconductor
Hynix Semiconductor
GM71C4400CL

1M x 4 Bit CMOS DRAM

Hynix Semiconductor
Hynix Semiconductor

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