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D6600A PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 D6600A
기능 UPD6600A
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D6600A 데이터시트, 핀배열, 회로
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD6124A, 6600A
4-BIT SINGLE-CHIP MICROCONTROLLER
FOR REMOTE CONTROL TRANSMISSION
DESCRIPTION
The µPD6124A and 6600A are 4-bit single-chip microcontrollers for infrared remote controllers for TVs, VCRs,
stereos, cassette decks, air conditions, etc.
www.DataSheet4U.comThese microcontrollers consist of ROM, RAM, a 4-bit parallel-processing ALU, a programmable timer, key input/
output ports, and transmit output ports. Functioning is controlled by a program.
A one-time PROM, model µPD61P24, to which a program can be written only once is also available. This one-time
PROM is ideal for evaluation of programs running in a µPD6124A or 6600A, and for small-scale production of such
systems.
FEATURES
Transmitter for programmable infrared remote control-
ler
19 types of instructions
Instruction execution time: 17.6 µs (with 455-kHz ce-
ramic resonator)
Program memory (ROM) capacity
µPD6124A: 1002 × 10 bits
µPD6600A: 512 × 10 bits
Data memory (RAM) capacity: 32 × 5 bits
9-bit programmable timer: 1 channel
I/O pins (KI/O): 8 pins
Input pins (KI): 4 pins
Serial input pins (S-IN): 1 pin
Transmission-in-progress indication pin (S-OUT): 1
pin
Transmit carrier frequency (REM)
fOSC/12, fOSC/8
Standby operation (HALT/STOP mode)
Low power consumption
Current consumption in STOP mode (TA = 25°C)
Low-voltage operation
µPD6124A: VDD = 2.2 to 5.5 V
µPD6600A: VDD = 2.2 to 3.6 V
Caution To use the NEC transmission format, ask NEC to supply the custom code.
Do not use R0 when using a register as an operand of the branch instruction.
The information in this document is subject to change without notice.
Document No. U12391EJ5V0DS00 (5th edition)
(Previous No. IC-1927)
Date Published June 1997 N
Printed in Japan
The mark shows major revised points.
© 1989




D6600A pdf, 반도체, 판매, 대치품
µPD6124A, 6600A
1. PROGRAM COUNTER (PC) ……… 9 BITS : µPD6600A
10 BITS : µPD6124A
The program counter (PC) is a binary counter, which holds the address information for the program memory.
Figure 1-1. Program Counter Organization
(a) µ PD6600A
PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 PC
www.DataSheet4U.com
(b) µPD6124A
PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 PC
Normally, the program counter contents are automatically incremented each time an instruction is executed,
according to the number of instruction bytes.
When executing a jump instruction (JMP0, JC, JF), the program counter indicates the jump destination.
Immediate data or the data memory contents are loaded to all or some bits of the PC.
When executing the call instruction (CALL0), the PC contents are incremented (+1) and saved into the stack memory.
Then, a value needed for each jump instruction will be loaded.
When executing the return instruction (RET), the stack memory contents are double incremented (+2) and loaded
into the PC.
When “all clear” is input or on reset, the PC contents are cleared to “000H”.
2. STACK POINTER (SP) ……… 2 BITS
This 2-bit register holds the start address information for the stack area. The stack area is shared with the data
memory.
The SP contents are incremented, when the call instruction (CALL0) is executed. They are decremented, when the
return instruction (RET) is executed.
The stack pointer is cleared to “00B” after reset or “all clear” is input, and indicates the highest address FH for the
data memory as the stack area.
The figure below shows the relationship for the stack pointer and the data memory area.
Data memory
(SP)
RC 11B
RD 10B
RE 01B
RF 00B
If the stack pointer overflows or underflows, it is determined that the CPU overflows, and the PC internal reset signal
will be generated.
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D6600A 전자부품, 판매, 대치품
µPD6124A, 6600A
9. SYSTEM CLOCK GENERATOR
The system clock generator consists of a resonator, which uses a ceramic resonator (400kHz to 500kHz).
Figure 9-1. System Clock Generator
OSC-IN
STOP mode
www.DataSheet4U.com
OSC-OUT
ø
System clock
In the STOP mode (oscillation stop HALT instruction), the oscillator in the system clock generator stops its operation,
and the system clock ø is stopped.
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