|
|
Número de pieza | MC14LC5540 | |
Descripción | ADPCM Codec | |
Fabricantes | Motorola Semiconductors | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de MC14LC5540 (archivo pdf) en la parte inferior de esta página. Total 18 Páginas | ||
No Preview Available ! MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Technical Summary
ADPCM Codec
This technical summary provides a brief description of the MC14LC5540
ADPCM Codec. A complete data book for the MC14LC5540 is available and
can be ordered from your local Motorola sales office. The data book number is
MC145540/D.
The MC14LC5540 ADPCM Codec is a single chip implementation of a PCM
Codec–Filter and an ADPCM encoder/decoder, and therefore provides an
efficient solution for applications requiring the digitization and compression of
voiceband signals. This device is designed to operate over a wide voltage
range, 2.7 to 5.25 V and, as such, is ideal for battery powered as well as ac
powered applications. The MC14LC5540 ADPCM Codec also includes a serial
control port and internal control and status registers that permit a microcom-
puter to exercise many built–in features.
The ADPCM Codec is designed to meet the 32 kbps ADPCM conformance
requirements of CCITT Recommendation G.721–1988 and ANSI T1.301. It
also meets ANSI T1.303 and CCITT Recommendation G.723–1988 for 24 kbps
ADPCM operation, and the 16 kbps ADPCM standard, CCITT Recommen-
dation G.726. This device also meets the PCM conformance specification of the
CCITT G.714 Recommendation.
• Single 2.7 to 5.25 V Power Supply
• Typical 2.7 V Power Dissipation of 43 mW, Power–Down of 15 µW
• Differential Analog Circuit Design for Lowest Noise
• Complete Mu–Law and A–Law Companding PCM Codec–Filter
• ADPCM Transcoder for 64, 32, 24, and 16 kbps Data Rates
• Universal Programmable Dual Tone Generator
• Programmable Transmit Gain, Receive Gain, and Sidetone Gain
• Low Noise, High Gain, Three Terminal Input Operational Amplifier for
Microphone Interface
• Push–Pull, 300 Ω Power Drivers with External Gain Adjust for Receiver
Interface
• Push–Pull, 300 Ω Auxiliary Output Drivers for Ringer Interface
• Voltage Regulated Charge Pump to Power the Analog Circuitry in Low
Voltage Applications
• Receive Noise Burst Detect Algorithm
• Order Complete Document as MC145540/D
• Device Supported by MC145537EVK ADPCM Codec Evaluation Kit
Order this document
by MC14LC5540TS/D
MC14LC5540
28
1
P SUFFIX
PLASTIC DIP
CASE 710
28
1
DW SUFFIX
SOG PACKAGE
CASE 751F
32 1
FU SUFFIX
TQFP
CASE 873A
ORDERING INFORMATION
MC14LC5540P Plastic DIP
MC14LC5540DW SOG Package
MC14LC5540FU TQFP
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
REV 2
6/97 TN97060200
©MOMoTtoOroRla,OInLc.A1997
MC14LC5540
1
1 page BCLKR
Bit Clock, Receive (PDIP, SOG, TQFP—Pin 26)
When used in the Long Frame Sync or Short Frame Sync
mode, this pin accepts any bit clock frequency from 64 to
5120 kHz. This pin may be used for applying an external
256 kHz clock for sequencing the analog signal processing
functions of this device. This is selected by the SCP port at
BR0 (b7).
FSR
Frame Sync, Receive (PDIP, SOG, TQFP—Pin 27)
When used in the Long Frame Sync or Short Frame Sync
mode, this pin accepts an 8 kHz clock that synchronizes the
input of the serial ADPCM data at the DR pin. FSR can oper-
ate asynchronous to FST in the Long Frame Sync or Short
Frame Sync mode.
SERIAL CONTROL PORT INTERFACE PINS
PDI/RESET
Power–Down Input/Reset
(PDIP, SOG—Pin 13; TQFP—Pin 11)
A logic 0 applied to this input forces the device into a low–
power dissipation mode. A rising edge on this pin causes
power to be restored and the ADPCM Reset state (specified
in the standards) to be forced.
SCPEN
Serial Control Port Enable Input
(PDIP, SOG—Pin 14; TQFP—Pin 12)
This pin, when held low, selects the Serial Control Port
(SCP) for the transfer of control and status information into
and out of the MC14LC5540 ADPCM Codec. This pin should
be held low for a total of 16 periods of the SCPCLK signal in
order for information to be transferred into or out of the
MC14LC5540 ADPCM Codec. The timing relationship be-
tween SCPEN and SCPCLK is shown in Figures 6 through 9.
SCPCLK
Serial Control Port Clock Input
(PDIP, SOG—Pin 15; TQFP—Pin 13)
This input to the device is used for controlling the rate of
transfer of data into and out of the SCP Interface. Data are
clocked into the MC14LC5540 ADPCM Codec from SCP Rx
on rising edges of SCPCLK. Data are shifted out of the de-
vice on SCP Tx on falling edges of SCPCLK. SCPCLK can
be any frequency from 0 to 4.096 MHz. An SCP transaction
takes place when SCPEN is brought low. Note that SCPCLK
is ignored when SCPEN is high ( i.e., it may be continuous or
it can operate in a burst mode).
SCP Tx
Serial Control Port Transmit Output
(PDIP, SOG—Pin 16; TQFP—Pin 14)
SCP Tx is used to output control and status information
from the MC14LC5540 ADPCM Codec. Data are shifted out
of SCP Tx on the falling edges of SCPCLK, most significant
bit first.
SCP Rx
Serial Control Port Receive Input
(PDIP, SOG—Pin 17; TQFP—Pin 15)
SCP Rx is used to input control and status information to
the MC14LC5540 ADPCM Codec. Data are shifted into the
device on rising edges of SCPCLK. SCP Rx is ignored when
data are being shifted out of SCP Tx or when SCPEN is
high.
MOTOROLA
MC14LC5540
5
5 Page connecting the external 0.1 µF capacitor (C1) between the
VEXT power supply pin and the power supply ground pin,
VSS. This puts a charge of as much as 2.7 V on C1. The
charge pump circuitry then connects the negative lead of C1
to the VEXT, pin which sums the voltage of C1 with the volt-
age at VEXT for a minimum potential voltage of 5.4 V. The
charge voltage on C1 is regulated such that the summing of
voltages is regulated to 5 V. This limits all of the voltages on
the device to safe levels for this IC fabrication technology.
This charge pumped voltage is then stored on the 1.0 µF ca-
pacitor connected at VDD and VSS, which filters and serves
as a reservoir for power. The clock period for this charge
pump is the same 256 kHz as the analog sequencing clock,
minimizing noise problems.
For applications with a regulated 5 V (± 5%) power supply,
the VDD pin and the VEXT pin are connected to the 5 V power
supply. These pins may share one decoupling capacitor in
this configuration as a function of external noise on the
power supply. The on–chip, 5 V regulated charge pump
should be turned off via the SCP port at register 0. The
external capacitor (C1) should not be populated for these
applications.
Digital Signal Processing Power Supply
This device has an on–chip series regulator which limits
the voltage of the Digital Signal Processing (DSP) circuitry to
about 2.3 V. This reduces the maximum power dissipation of
this circuitry. From the VEXT power supply pin, the DSP cir-
cuitry appears as a constant current load instead of a resis-
tive (CV2/2) load for a constant clock frequency. This series
regulator is designed to have a low drop–out voltage, which
allows the DSP circuitry to work when the VEXT voltage is as
low as 2.7 V. The output of this regulator is brought out to the
VDSP pin for a 0.1 µF decoupling capacitor. This regulator is
not designed to power any loads external to the device.
ANALOG INTERFACE AND SIGNAL PATH
Transmit Analog
The transmit analog portion of this device includes a low–
noise, three terminal operational amplifier capable of driving
a 2 kΩ load. This op amp has inputs of TI+ and TI– and its
output is TG. This op amp is intended to be configured in an
inverting gain circuit. The analog signal may be applied di-
rectly to the TG pin if this transmit op amp is independently
powered down. Power–down may be achieved by connect-
ing both the TI+ and TI– inputs to the VDD pin. The TG pin
becomes high impedance when the transmit op amp is pow-
ered down. The TG pin is internally connected to a time con-
tinuous three–pole anti–aliasing pre–filter. This pre–filter
incorporates a two–pole Butterworth active low–pass filter,
followed by a single passive pole. This pre–filter is followed
by a single–ended to differential converter that is clocked at
512 kHz. All subsequent analog processing utilizes fully dif-
ferential circuitry. The output of the differential converter is
followed by the transmit trim gain stage. This stage is in-
tended to compensate for gain tolerances of external compo-
nents such as microphones. The amount of gain control is
0–7 dB in 1 dB steps. This stage only accommodates posi-
tive gain because the maximum signal levels of the output of
the input op amp are the same as the transmit filter and ADC,
which should nominally be next to the clip levels of this de-
vice’s circuitry. Any requirement for attenuation of the output
of the input op amp would mean that it is being overdriven.
The gain is programmed via the SCP port in BR1 (b2:b0).
The next section is a fully–differential, 5–pole switched–ca-
pacitor low–pass filter with a 3.4 kHz frequency cutoff. After
this filter is a 3–pole switched–capacitor high–pass filter hav-
ing a cutoff frequency of about 200 Hz. This high–pass stage
has a transmission zero at dc that eliminates any dc coming
from the analog input or from accumulated op amp offsets in
the preceding filter stages. (This high–pass filter may be re-
moved from the signal path under control of the SCP port
BR8 (b4).) The last stage of the high–pass filter is an auto-
zeroed sample and hold amplifier.
One bandgap voltage reference generator and digital–to–
analog converter (DAC) are shared by the transmit and
receive sections. The autozeroed, switched–capacitor band-
gap reference generates precise positive and negative refer-
ence voltages that are virtually independent of temperature
and power supply voltage. A binary–weighted capacitor
array (CDAC) forms the chords of the companding structure,
while a resistor string (RDAC) implements the linear steps
within each chord. The encode process uses the DAC, the
voltage reference, and a frame–by–frame autozeroed
comparator to implement a successive–approximation ana-
log–to–digital conversion (ADC) algorithm. All of the analog
circuitry involved in the data conversion (the voltage refer-
ence, RDAC, CDAC, and comparator) are implemented with
a differential architecture.
The nonlinear companded Mu–Law transfer curve of the
ADC may be changed to 8–bit linear by BR8 (b5).
The input to the ADC is normally connected to the output
of the transmit filter section, but may be switched to measure
the voltage at the VEXT pin for battery voltage monitoring.
This is selected by the I/O Mode in BR0 (b4:b3). In this
mode, the ADC is programmed to output a linear 8–bit PCM
word for the voltage at VEXT which is intended to be read in
BR9 (b7:b0). The data format for the ADC output is a “Don’t
Care” for the sign bit and seven magnitude bits. The scaling
for the ADC is for 6.3 V at VEXT equals full scale (BIN X111
1111). The ADPCM algorithm does not support dc signals.
Transmit Digital
The Digital Signal Processor (DSP) section of this device
is a custom designed, interrupt driven, microcoded machine
optimized for implementing the ADPCM algorithms. In the
full–duplex speech mode, the DSP services one encode in-
terrupt and one decode interrupt per frame (125 µs). The en-
code algorithm (i.e., 16 kbps, 24 kbps, or 32 kbps ADPCM, or
64 kbps PCM) is determined by the length of the transmit
output enable at the FST pin. The length of the FST enable
measured in transmit data clock (BCLKT) cycles tells the de-
vice which encoding rate to use. This enable length informa-
tion is used by the encoder each frame. The transmit
ADPCM word corresponding to this request will be computed
during the next frame and will be available a total of two
frames after being requested. This transmit enable length in-
formation can be delayed by the device an additional four
frames corresponding to a total of six frames. These six
frames of delay allow the device to be clocked with the same
clocks for both transmit (encode) and receive (decode), and
to be frame aligned for applications that require every sixth
frame signaling. It is important to note that the enable length
information is delayed and not the actual ADPCM (PCM)
sample word. The amount of delay for the FST enable length
MOTOROLA
MC14LC5540
11
11 Page |
Páginas | Total 18 Páginas | |
PDF Descargar | [ Datasheet MC14LC5540.PDF ] |
Número de pieza | Descripción | Fabricantes |
MC14LC5540 | ADPCM Codec | Motorola Semiconductors |
Número de pieza | Descripción | Fabricantes |
SLA6805M | High Voltage 3 phase Motor Driver IC. |
Sanken |
SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
Analog Devices |
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |