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MC14LC5004 데이터시트 PDF




Motorola Semiconductors에서 제조한 전자 부품 MC14LC5004은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


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부품번호 MC14LC5004 기능
기능 (MC14LC5003 / MC14LC5004) 128 Segment LCD Drivers
제조업체 Motorola Semiconductors
로고 Motorola Semiconductors 로고


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MC14LC5004 데이터시트, 핀배열, 회로
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
128 Segment LCD Drivers
CMOS
The MC14LC5003/5004 are 128-segment, multiplexed-by-four LCD Driv-
ers. The two devices are functionally the same except for their data input
protocols. The MC14LC5003 uses a serial interface data input protocol. The
device may be interfaced to the MC68HCXX product families using a minimal
amount of software (see example). The MC14LC5004 has a IIC interface and
has essentially the same protocol, except that the device sends an acknowl-
edge bit back to the transmitter after each eight-bit byte is received.
MC14LC5004 also has a “read mode”, whereby data sent to the device may
be retrieved via the IIC bus.
The MC14LC5003/MC14LC5004 drives the liquid-crystal displays in a mul-
tiplexed-by-four configuration. The device accepts data from a microproces-
sor or other serial data source to drive one segment per bit. The chip does
not have a decoder, allowing for the flexibility of formatting the segment data
externally.
Devices are independently addressable via a two-wire (or three-wire) com-
munication link which can be common with other peripheral devices.
The MC14LC5003/MC14LC5004 are low cost version of MC145003 and
MC145004 without cascading function.
Drives 128 Segments Per Package
May Be Used with the Following LCDs: Segmented Alphanumeric,
Bar Graph, Dot Matrix, Custom
Quiescent Supply Current: 30 A @ 2.7 V VDD
Operating Voltage Range: 2.7 to 5.5 V
Operating Temperature Range: - 40 to 85C
Separate Access to LCD Drive Section’s Supply Voltage to Allow for Tem-
perature Compensation
See Application Notes AN1066 and AN442
MC14LC5003
MC14LC5004
52 1
QFP
FU SUFFIX
CASE 848B
ORDERING INFORMATION
MC14LC5003FU QFP
MC14LC5004FU QFP
MCC14LC5003 BARE DIE
MCC14LC5004 BARE DIE
PIN ASSIGNMENT
FP32
FP31
FP30
FP29
FP28
FP27
FP26
FP25
FP24
FP23
FP22
FP21
FP20
52 51 50 49 48 47 46 45 44 43 42 41 40
1 39
2 38
3 37
4 36
5 35
6 34
7 33
8 32
9 31
10 30
11 29
12 28
13 27
14 15 16 17 18 19 20 21 22 23 24 25 26
Din
DCLK
NC
FP1
FP2
FP3
FP4
FP5
FP6
FP7
FP8
FP9
FP10
OSC1
OSC2
BLOCK DIAGRAM
BP1-BP4
VLCD
OSCILLATOR
DRIVERS
FP1-FP32
DRIVERS
NC=NO CONNECTION
DCLK
Din
A0
A1
A2
ENB
FRAME
SYNC
GENERATOR
POR
LCD VOLTAGE
WAVEFORM
AND TIMING
GENERATOR
128 - 32
MULTIPLEX
128-BIT LATCH
128-BIT SHIFT REGISTER
REV 2
10/96
MOTOROLA
MC14LC5003 • MC14LC5004
3–3




MC14LC5004 pdf, 반도체, 판매, 대치품
SWITCHING WAVEFORMS
90%
CLK 50%
10%
tf tr
tw tw
Figure 1.
ENB
CLK
VDD
GND
VALID
Din 50%
tsu th
CLK 50%
Figure 2.
50%
tsu
tw
th
50%
FIRST
CLK
LAST
CLK
Figure 3.
tw
trec
VDD
GND
VDD
GND
VDD
GND
VDD
GND
MC14LC5003 • MC14LC5004
3–6
MOTOROLA

4페이지










MC14LC5004 전자부품, 판매, 대치품
PIN DESCRIPTIONS
A0-A2
Address Inputs (Pins 42-44)
The devices have to receive a correct address before they
will accept data. Three address pins (A2, A1, A0) are used to
define the states of the three programmable bits of
MC14LC5003/MC14LC5004’s 8-bit address.
The address is 0111vwxy where v, w, x represent A2, A1,
and A0 respectively. Where v, w, x=0, then A2, A1, and A0
should be tied to 0 V. Where v, w, x=1, then A2, A1, and A0
should be tied to VDD.
The address pins must be tied to VDD. This defines the
device as a master.
NOTE
Note: In applications where the circuit will be isolated from
external manual interference the system designer may take
advantage of the self-programming feature. Upon power-on,
address pins which are left open-circuit will be charged to VDD.
However, care must be taken not to inadvertently discharge
the pins after power-on since the address may then be lost. A
similar feature is also available on the ENB pin.
10 M
1M
100 k
10 k
1k
10 k 100 k 1 M
OSCILLATOR FREQUENCY
10 M
Figure 6. Oscillator Frequency vs. Load Resistance
(Approximate)
FP1-FP32
Frontplane Drivers (Pins 36-27, 25-22, 19-15, 13-1)
Frontplane driver outputs.
CAUTION
The configuration A0, A1, A2 = 000 should not be used. This
does not give a valid address and is reserved for Motorola’s
use only. All three address pins should never be tied to 0 V
simultaneously.
ENB
Enable Input (Pin 41)
If the ENB pin is tied to VDD, the MC14LC5003/
MC14LC5004 will always latch the data after 128 bits have
been received. The latched data is multiplexed and fed to the
frontplane drivers for display. If external control of this latching
function is required, then the ENB pin should be held low,
followed by one high pulse on ENB when data display is re-
quired. (This may be useful in a system where one MC145003/
MC145004 is permanently addressed and only the last 128
bits of data sent are required to be latched for display). The
pulse on the ENB pin must occur while DCLK is high.
DCLK, Din
Data Clock and Data Input (Pins 38, 39)
Address input and data input controls. See Data Input Pro-
tocol sections for relevant option.
BP1-BP4
Backplane Drivers (Pins 48-45)
Backplane driver outputs.
VLCD
LCD Driver Supply (Pin 20)
Power supply input for LCD drive outputs. May be used to
supply a temperature-compensated voltage to the LCD drive
section, which can be separate from the logic voltage supply,
VDD.
VDD
Positive Power Supply (Pin 49)
This pin supplies power to the main processor interface and
logic portions of the device. The voltage range is 2.7 to 5.5 V
with respect to the VSS pin.
For optimum performance, VDD should be bypassed to
VSS using a low inductance capacitor mounted very closely
to these pins. Lead length on this capacitor should be mini-
mized.
VSS
Ground (Pin 21)
Common ground.
OSC1, OSC2
Oscillator Pins (Pins 51, 50)
To use the on-board oscillator, an external resistor should
be connected between OSC1 and OSC2. Optionally, the
OSC1 pin may be driven by an externally generated clock
signal.
A resistor of 680 k connected between OSC1 and OSC2
pins gives an oscillator frequency of about 30 kHz, giving
approximately 30 Hz as seen at the LCD driver outputs. A
resistor of 200 k gives about 100 kHz, which results in 100Hz
at the driver outputs. LCD manufacturers recommend an LCD
drive frequency of between 30 Hz and 100 Hz. See Figure 6.
DATA INPUT PROTOCOL
Two-wire communication bus DCLK, Din; three-wire com-
munication bus DCLK, Din, ENB.
MC14LC5003 — SERIAL INTERFACE DEVICE (FIGURE 7)
Before communication with an MC14LC5003 can begin, a
start condition must be set up on the bus by the transmitter.
To establish a start condition, the transmitter must pull the
data line low while the clock line is high. The “idle” state for
the clock line and data line is the high state.
After the start condition has been established, an eight-bit
address should be sent by the transmitter. If the address sent
corresponds to the address of the MC14LC5003 then on each
MOTOROLA
MC14LC5003 • MC14LC5004
3–9

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