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기능 5 V PCM Codec-Filter
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MC14LC5480 데이터시트, 핀배열, 회로
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MC14LC5480/D
Advance Information
5 V PCM Codec-Filter
The MC14LC5480 is a general purpose per channel PCM Codec–Filter with
pin selectable Mu–Law or A–Law companding, and is offered in 20–pin DIP,
SOG, and SSOP packages. This device performs the voice digitization and
reconstruction as well as the band limiting and smoothing required for PCM
systems. This device is designed to operate in both synchronous and
asynchronous applications and contains an on–chip precision reference
voltage.
This device has an input operational amplifier whose output is the input to the
encoder section. The encoder section immediately low–pass filters the analog
signal with an active R–C filter to eliminate very high frequency noise from being
modulated down to the passband by the switched capacitor filter. From the
active R–C filter, the analog signal is converted to a differential signal. From this
point, all analog signal processing is done differentially. This allows processing
of an analog signal that is twice the amplitude allowed by a single–ended
design, which reduces the significance of noise to both the inverted and
non–inverted signal paths. Another advantage of this differential design is that
noise injected via the power supplies is a common–mode signal that is
cancelled when the inverted and non–inverted signals are recombined. This
dramatically improves the power supply rejection ratio.
After the differential converter, a differential switched capacitor filter band–
passes the analog signal from 200 Hz to 3400 Hz before the signal is digitized
by the differential compressing A/D converter.
The decoder accepts PCM data and expands it using a differential D/A
converter. The output of the D/A is low–pass filtered at 3400 Hz and sinX/X
compensated by a differential switched capacitor filter. The signal is then filtered
by an active R–C filter to eliminate the out–of–band energy of the switched
capacitor filter.
The MC14LC5480 PCM Codec–Filter accepts a variety of clock formats,
including Short Frame Sync, Long Frame Sync, IDL, and GCI timing
environments. This device also maintains compatibility with Motorola’s family of
Telecommunication products, including the MC14LC5472 U–Interface Trans-
ceiver, MC145474/75 S/T–Interface Transceiver, MC145532 ADPCM Trans-
coder, MC145422/26 UDLT–1, MC145421/25 UDLT–2, and MC3419/MC33120
SLIC.
The MC14LC5480 PCM Codec–Filter utilizes CMOS due to its reliable
low–power performance and proven capability for complex analog/digital VLSI
functions.
Pin for Pin Replacement for the MC145480
Single 5 V Power Supply
Typical Power Dissipation of 15 mW, Power–Down of 0.01 mW
Fully–Differential Analog Circuit Design for Lowest Noise
Transmit Band–Pass and Receive Low–Pass Filters On–Chip
Active R–C Pre–Filtering and Post–Filtering
Mu–Law and A–Law Companding by Pin Selection
On–Chip Precision Reference Voltage (1.575 V)
Push–Pull 300 Power Drivers with External Gain Adjust
MC145536EVK is the Evaluation Kit that Also Includes the MC145532
ADPCM Transcoder
MC14LC5480
20
1
20
1
P SUFFIX
PLASTIC DIP
CASE 738
DW SUFFIX
SOG PACKAGE
CASE 751D
SD SUFFIX
SSOP
20 CASE 940C
1
ORDERING INFORMATION
MC14LC5480P Plastic DIP
MC14LC5480DW SOG Package
MC14LC5480SD SSOP
PIN ASSIGNMENT
RO+
RO–
PI
PO–
PO+
VDD
FSR
DR
BCLKR
PDI
1
2
3
4
5
6
7
8
9
10
20 VAG
19 TI+
18 TI–
17 TG
16 Mu/A
15 VSS
14 FST
13 DT
12 BCLKT
11 MCLK
This document contains information on a new product. Specifications and information herein are subject to change without notice.
REV 0.1
5/96
©MOMoTtoOroRla,OInLc.A1996
MC14LC5480
1




MC14LC5480 pdf, 반도체, 판매, 대치품
therefore low impedance loads must be between PO+ and
PO–. Connecting PI to VDD will power down the power driver
amplifiers and the PO+ and PO– outputs will be high imped-
ance. This pin is also high impedance when the device is
powered down by the PDI pin.
PO+
Power Amplifier Output (Non–Inverting) (Pin 5)
This is the non–inverting power amplifier output, which is
an inverted version of the signal at PO–. This pin is capable
of driving a 300 load to PO–. Connecting PI to VDD will
power down the power driver amplifiers and the PO+ and
PO– outputs will be high impedance. This pin is also high im-
pedance when the device is powered down by the PDI pin.
See PI and PO– for more information.
DIGITAL INTERFACE
MCLK
Master Clock (Pin 11)
This is the master clock input pin. The clock signal applied
to this pin is used to generate the internal 256 kHz clock and
sequencing signals for the switched–capacitor filters, ADC,
and DAC. The internal prescaler logic compares the clock on
this pin to the clock at FST (8 kHz) and will automatically
accept 256, 512, 1536, 1544, 2048, 2560, or 4096 kHz. For
MCLK frequencies of 256 and 512 kHz, MCLK must be syn-
chronous and approximately rising edge aligned to FST. For
optimum performance at frequencies of 1.536 MHz and
higher, MCLK should be synchronous and approximately ris-
ing edge aligned to the rising edge of FST. In many ap-
plications, MCLK may be tied to the BCLKT pin.
FST
Frame Sync, Transmit (Pin 14)
This pin accepts an 8 kHz clock that synchronizes the out-
put of the serial PCM data at the DT pin. This input is com-
patible with various standards including IDL, Long Frame
Sync, Short Frame Sync, and GCI formats. If both FST and
FSR are held low for several 8 kHz frames, the device will
power down.
BCLKT
Bit Clock, Transmit (Pin 12)
This pin controls the transfer rate of transmit PCM data. In
the IDL and GCI modes it also controls the transfer rate of
the receive PCM data. This pin can accept any bit clock fre-
quency from 64 to 4096 kHz for Long Frame Sync and Short
Frame Sync timing. This pin can accept clock frequencies
from 256 kHz to 4.096 MHz in IDL mode, and from 512 kHz
to 6.176 MHz for GCI timing mode.
DT
Data, Transmit (Pin 13)
This pin is controlled by FST and BCLKT and is high im-
pedance except when outputting PCM data. When operating
in the IDL or GCI mode, data is output in either the B1 or B2
channel as selected by FSR. This pin is high impedance
when the device is in the powered down mode.
MC14LC5480
4
FSR
Frame Sync, Receive (Pin 7)
When used in the Long Frame Sync or Short Frame Sync
mode, this pin accepts an 8 kHz clock, which synchronizes
the input of the serial PCM data at the DR pin. FSR can be
asynchronous to FST in the Long Frame Sync or Short
Frame Sync modes. When an ISDN mode (IDL or GCI) has
been selected with BCLKR, this pin selects either B1 (logic 0)
or B2 (logic 1) as the active data channel.
BCLKR
Bit Clock, Receive (Pin 9)
When used in the Long Frame Sync or Short Frame Sync
mode, this pin accepts any bit clock frequency from 64 to
4096 kHz. When this pin is held at a logic 1, FST, BCLKT, DT,
and DR become IDL Interface compatible. When this pin is
held at a logic 0, FST, BCLKT, DT, and DR become GCI Inter-
face compatible.
DR
Data, Receive (Pin 8)
This pin is the PCM data input, and when in a Long Frame
Sync or Short Frame Sync mode is controlled by FSR and
BCLKR. When in the IDL or GCI mode, this data transfer is
controlled by FST and BCLKT. FSR and BCLKR select the
B channel and ISDN mode, respectively.
FUNCTIONAL DESCRIPTION
ANALOG INTERFACE AND SIGNAL PATH
The transmit portion of this device includes a low–noise,
three–terminal op amp capable of driving a 2 kload. This
op amp has inputs of TI+ (Pin 19) and TI– (Pin 18) and its
output is TG (Pin 17). This op amp is intended to be confi-
gured in an inverting gain circuit. The analog signal may be
applied directly to the TG pin if this transmit op amp is inde-
pendently powered down by connecting the TI+ and TI–
inputs to the VDD power supply. The TG pin becomes high
impedance when the transmit op amp is powered down. The
TG pin is internally connected to a 3–pole anti–aliasing pre–
filter. This pre–filter incorporates a 2–pole Butterworth active
low–pass filter, followed by a single passive pole. This pre–
filter is followed by a single–ended to differential converter
that is clocked at 512 kHz. All subsequent analog processing
utilizes fully–differential circuitry. The next section is a fully–
differential, 5–pole switched–capacitor low–pass filter with a
3.4 kHz frequency cutoff. After this filter is a 3–pole
switched–capacitor high–pass filter having a cutoff fre-
quency of about 200 Hz. This high–pass stage has a trans-
mission zero at dc that eliminates any dc coming from the
analog input or from accumulated op amp offsets in the pre-
ceding filter stages. The last stage of the high–pass filter is
an autozeroed sample and hold amplifier.
One bandgap voltage reference generator and digital–to–
analog converter (DAC) are shared by the transmit and re-
ceive sections. The autozeroed, switched–capacitor
bandgap reference generates precise positive and negative
reference voltages that are virtually independent of tempera-
ture and power supply voltage. A binary–weighted capacitor
array (CDAC) forms the chords of the companding structure,
while a resistor string (RDAC) implements the linear steps
within each chord. The encode process uses the DAC, the
voltage reference, and a frame–by–frame autozeroed
comparator to implement a successive–approximation con-
MOTOROLA

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MC14LC5480 전자부품, 판매, 대치품
Long Frame Sync
Long Frame Sync is the industry name for one type of
clocking format that controls the transfer of the PCM data
words. (Refer to Figure 2a.) The ‘‘Frame Sync’’ or ‘‘Enable’’ is
used for two specific synchronizing functions. The first is to
synchronize the PCM data word transfer, and the second is
to control the internal analog–to–digital and digital–to–analog
conversions. The term ‘‘Sync’’ refers to the function of syn-
chronizing the PCM data word onto or off of the multiplexed
serial PCM data bus, which is also known as a PCM high-
way. The term ‘‘Long’’ comes from the duration of the frame
sync measured in PCM data clock cycles. Long Frame Sync
timing occurs when the frame sync is used directly as the
PCM data output driver enable. This results in the PCM out-
put going low impedance with the rising edge of the transmit
frame sync, and remaining low impedance for the duration of
the transmit frame sync.
The implementation of Long Frame Sync has maintained
compatibility and been optimized for external clocking sim-
plicity. This optimization includes the PCM data output going
low impedance with the logical AND of the transmit frame
sync (FST) with the transmit data bit clock (BCLKT). The op-
timization also includes the PCM data output (DT) remaining
low impedance until the middle of the LSB (seven and a half
PCM data clock cycles) or until the FST pin is taken low,
whichever occurs last. This requires the frame sync to be
approximately rising edge aligned with the initiation of the
PCM data word transfer, but the frame sync does not have a
precise timing requirement for the end of the PCM data word
transfer. The device recognizes Long Frame Sync clocking
when the frame sync is held high for two consecutive falling
edges of the transmit data clock. The transmit logic decides
on each frame sync whether it should interpret the next
frame sync pulse as a Long or a Short Frame Sync. This de-
cision is used for receive circuitry also. The device is de-
signed to prevent PCM bus contention by not allowing the
PCM data output to go low impedance for at least two frame
sync cycles after power is applied or when coming out of the
powered down mode.
The receive side of the device is designed to accept the
same frame sync and data clock as the transmit side and to
be able to latch its own transmit PCM data word. Thus the
PCM digital switch needs to be able to generate only one
type of frame sync for use by both transmit and receive sec-
tions of the device.
The logical AND of the receive frame sync with the receive
data clock tells the device to start latching the 8–bit serial
word into the receive data input on the falling edges of the
receive data clock. The internal receive logic counts the re-
ceive data clock cycles and transfers the PCM data word to
the digital–to–analog converter sequencer on the ninth data
clock rising edge.
This device is compatible with four digital interface modes.
To ensure that this device does not reprogram itself for a dif-
ferent timing mode, the BCLKR pin must change logic state
no less than every 125 µs. The minimum PCM data bit clock
frequency of 64 kHz satisfies this requirement.
Short Frame Sync
Short Frame Sync is the industry name for the type of
clocking format that controls the transfer of the PCM data
words (refer to Figure 2b). The ‘‘Frame Sync’’ or ‘‘Enable’’ is
used for two specific synchronizing functions. The first is to
synchronize the PCM data word transfer, and the second is
to control the internal analog–to–digital and digital–to–analog
conversions. The term ‘‘Sync’’ refers to the function of syn-
chronizing the PCM data word onto or off of the multiplexed
serial PCM data bus, which is also known as a PCM high-
way. The term ‘‘Short’’ comes from the duration of the frame
sync measured in PCM data clock cycles. Short Frame Sync
timing occurs when the frame sync is used as a ‘‘pre–syn-
chronization’’ pulse that is used to tell the internal logic to
clock out the PCM data word under complete control of the
data clock. The Short Frame Sync is held high for one falling
data clock edge. The device outputs the PCM data word be-
ginning with the following rising edge of the data clock. This
results in the PCM output going low impedance with the ris-
ing edge of the transmit data clock, and remaining low im-
pedance until the middle of the LSB (seven and a half PCM
data clock cycles).
The device recognizes Short Frame Sync clocking when
the frame sync is held high for one and only one falling edge
of the transmit data clock. The transmit logic decides on each
frame sync whether it should interpret the next frame sync
pulse as a Long or a Short Frame Sync. This decision is used
for receive circuitry also. The device is designed to prevent
PCM bus contention by not allowing the PCM data output to
go low impedance for at least two frame sync cycles after
power is applied or when coming out of the powered down
mode.
The receive side of the device is designed to accept the
same frame sync and data clock as the transmit side and to
be able to latch its own transmit PCM data word. Thus the
PCM digital switch needs to be able to generate only one
type of frame sync for use by both transmit and receive sec-
tions of the device.
The falling edge of the receive data clock latching a high
logic level at the receive frame sync input tells the device to
start latching the 8–bit serial word into the receive data input
on the following eight falling edges of the receive data clock.
The internal receive logic counts the receive data clock
cycles and transfers the PCM data word to the digital–to–
analog converter sequencer on the rising data clock edge af-
ter the LSB has been latched into the device.
This device is compatible with four digital interface modes.
To ensure that this device does not reprogram itself for a dif-
ferent timing mode, the BCLKR pin must change logic state
no less than every 125 µs. The minimum PCM data bit clock
frequency of 64 kHz satisfies this requirement.
Interchip Digital Link (IDL)
The Interchip Digital Link (IDL) Interface is one of two
standard synchronous 2B+D ISDN timing interface modes
with which this device is compatible. In the IDL mode, the de-
vice can communicate in either of the two 64 kbps B chan-
nels (refer to Figure 2c for sample timing). The IDL mode is
selected when the BCLKR pin is held high for two or more
FST (IDL SYNC) rising edges. The digital pins that control
the transmit and receive PCM word transfers are repro-
grammed to accommodate this mode. The pins affected are
FST, FSR, BCLKT, DT, and DR. The IDL Interface consists of
four pins: IDL SYNC (FST), IDL CLK (BCLKT), IDL TX (DT),
and IDL RX (DR). The IDL interface mode provides access to
both the transmit and receive PCM data words with common
control clocks of IDL Sync and IDL Clock. In this mode, the
MOTOROLA
MC14LC5480
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관련 데이터시트

부품번호상세설명 및 기능제조사
MC14LC5480

5 V PCM Codec-Filter

Motorola Semiconductors
Motorola Semiconductors
MC14LC5480

5 V PCM Codec-Filter

Motorola Semiconductors
Motorola Semiconductors

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