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PDF MC14LC5003 Data sheet ( Hoja de datos )
| Número de pieza | MC14LC5003 | |
| Descripción | (MC14LC5003 / MC14LC5004) 128 Segment LCD Drivers | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MC14LC5003 (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
128 Segment LCD Drivers
CMOS
The MC14LC5003/5004 are 128-segment, multiplexed-by-four LCD Driv-
ers. The two devices are functionally the same except for their data input
protocols. The MC14LC5003 uses a serial interface data input protocol. The
device may be interfaced to the MC68HCXX product families using a minimal
amount of software (see example). The MC14LC5004 has a IIC interface and
has essentially the same protocol, except that the device sends an acknowl-
edge bit back to the transmitter after each eight-bit byte is received.
MC14LC5004 also has a “read mode”, whereby data sent to the device may
be retrieved via the IIC bus.
The MC14LC5003/MC14LC5004 drives the liquid-crystal displays in a mul-
tiplexed-by-four configuration. The device accepts data from a microproces-
sor or other serial data source to drive one segment per bit. The chip does
not have a decoder, allowing for the flexibility of formatting the segment data
externally.
Devices are independently addressable via a two-wire (or three-wire) com-
munication link which can be common with other peripheral devices.
The MC14LC5003/MC14LC5004 are low cost version of MC145003 and
MC145004 without cascading function.
• Drives 128 Segments Per Package
• May Be Used with the Following LCDs: Segmented Alphanumeric,
Bar Graph, Dot Matrix, Custom
• Quiescent Supply Current: 30 A @ 2.7 V VDD
• Operating Voltage Range: 2.7 to 5.5 V
• Operating Temperature Range: - 40 to 85C
• Separate Access to LCD Drive Section’s Supply Voltage to Allow for Tem-
perature Compensation
• See Application Notes AN1066 and AN442
MC14LC5003
MC14LC5004
52 1
QFP
FU SUFFIX
CASE 848B
ORDERING INFORMATION
MC14LC5003FU QFP
MC14LC5004FU QFP
MCC14LC5003 BARE DIE
MCC14LC5004 BARE DIE
PIN ASSIGNMENT
FP32
FP31
FP30
FP29
FP28
FP27
FP26
FP25
FP24
FP23
FP22
FP21
FP20
52 51 50 49 48 47 46 45 44 43 42 41 40
1 39
2 38
3 37
4 36
5 35
6 34
7 33
8 32
9 31
10 30
11 29
12 28
13 27
14 15 16 17 18 19 20 21 22 23 24 25 26
Din
DCLK
NC
FP1
FP2
FP3
FP4
FP5
FP6
FP7
FP8
FP9
FP10
OSC1
OSC2
BLOCK DIAGRAM
BP1-BP4
VLCD
OSCILLATOR
DRIVERS
FP1-FP32
DRIVERS
NC=NO CONNECTION
DCLK
Din
A0
A1
A2
ENB
FRAME
SYNC
GENERATOR
POR
LCD VOLTAGE
WAVEFORM
AND TIMING
GENERATOR
128 - 32
MULTIPLEX
128-BIT LATCH
128-BIT SHIFT REGISTER
REV 2
10/96
MOTOROLA
MC14LC5003 • MC14LC5004
3–3
1 page  
FUNCTIONAL DESCRIPTION
The MC14LC5003/MC14LC5004 has essentially two sec-
tions which operate asynchronously from each other; the data
input and storage section and the LCD drive section. The LCD
drive and timing is derived from the oscillator, while the data
input and storage is controlled by the Data In (Din), Data Clock
(DCLK), Address (A0, A1, A2), and Enable (ENB) pins.
Data is shifted serially into the 128-bit shift register and ar-
ranged into four consecutive blocks of 32 parallel data bits. A
time-multiplex of the four backplane drivers is made (each
backplane driver becoming active then inactive one after an-
other) and, at the start of each backplane active period, the
corresponding block of 32 bits is made available at the front-
plane drivers. A high input to a plane driver turns the driver
on, and a low input turns the driver off.
Figure 4 shows the sequence of backplanes. Figure 5 shows
the possible configurations of the frontplanes relative to the
backplanes. When a backplane driver is on, its output switches
from VLCD to 0 V, and when it is off, it switches from 1/3 VLCD
to 2/3 VLCD. When a frontplane driver is on, its
output switches from 0 V to VLCD, and when it is off, it switches
from 2/3 VLCD to 1/3 VLCD.
The LCD drive and timing section provides the multiplex sig-
nals and backplane driver input signals and formats the front-
plane and backplane waveforms.
The address pins are used to uniquely distinguish LCD driver
from any other chips on the same bus and to define LCD driver
as the “master” in the system. There must be one master in any
system.
The enable pin may be used as a third control line in the
communication bus. It may be used to define the moment
when the data is latched. If not used, then the data is latched
after 128 bits of data have been received.
TIME FRAME
BP1
BP2
BP3
BP4
Figure 4. Backplane Sequence
VLCD
2/3 (VLCD)
1/3 (VLCD)
0V
VLCD
2/3 (VLCD)
1/3 (VLCD)
0V
VLCD
2/3 (VLCD)
1/3 (VLCD)
0V
VLCD
2/3 (VLCD)
1/3 (VLCD)
0V
MOTOROLA
MC14LC5003 • MC14LC5004
3–7
5 Page 
FP32
FP31
FP30
FP29
FP28
FP27
FP26
FP25
FP24
FP23
FP22
FP21
FP20
Din
DCLK
FP1
FP2
FP3
FP4
FP5
FP6
FP7
FP8
FP9
FP10
CONTROLLER
Figure 9. Application Example
MOTOROLA
MC14LC5003 • MC14LC5004
3–13
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet MC14LC5003.PDF ] | |
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