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부품번호 | MC7445 기능 |
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기능 | RISC Microprocessor Hardware Specifications | ||
제조업체 | Freescale Semiconductor | ||
로고 | |||
Freescale Semiconductor
Technical Data
MPC7455EC
Rev. 4.1, 02/2005
MPC7455
RISC Microprocessor
Hardware Specifications
The MPC7455 and MPC7445 are implementations of the
PowerPC™ microprocessor family of reduced instruction set
computer (RISC) microprocessors. This document is primarily
concerned with the MPC7455; however, unless otherwise noted,
all information here also applies to the MPC7445. This document
describes pertinent electrical and physical characteristics of the
MPC7455. For functional characteristics of the processor, refer to
the MPC7450 RISC Microprocessor Family User’s Manual. To
locate any published updates for this document, refer to the
website at http://www.freescale.com.
1 Overview
The MPC7455 is the third implementation of the fourth generation
(G4) microprocessors from Freescale. The MPC7455 implements
the full PowerPC 32-bit architecture and is targeted at networking
and computing systems applications. The MPC7455 consists of a
processor core, a 256-Kbyte L2, and an internal L3 tag and
controller which support a glueless backside L3 cache through a
dedicated high-bandwidth interface. The MPC7445 is identical to
the MPC7455 except it does not support the L3 cache interface.
Figure 1 shows a block diagram of the MPC7455.
Contents
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3. Comparison with the MPC7400, MPC7410,
MPC7450, MPC7451, and MPC7441 . . . . . . . . . . . . . 7
4. General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5. Electrical and Thermal Characteristics . . . . . . . . . . . 10
6. Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7. Pinout Listings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
8. Package Description . . . . . . . . . . . . . . . . . . . . . . . . . 41
9. System Design Information . . . . . . . . . . . . . . . . . . . 45
10. Document Revision History . . . . . . . . . . . . . . . . . . . 59
11. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 60
© Freescale Semiconductor, Inc., 2005. All rights reserved.
Features
– Thirty-two 64-bit FPRs for single- or double-precision operands
— Four vector units and 32-entry vector register file (VRs)
– Vector permute unit (VPU)
– Vector integer unit 1 (VIU1) handles short-latency AltiVec™ integer instructions, such as vector add
instructions (vaddsbs, vaddshs, and vaddsws, for example)
– Vector integer unit 2 (VIU2) handles longer-latency AltiVec integer instructions, such as vector
multiply add instructions (vmhaddshs, vmhraddshs, and vmladduhm, for example)
– Vector floating-point unit (VFPU)
— Three-stage load/store unit (LSU)
– Supports integer, floating-point, and vector instruction load/store traffic
– Four-entry vector touch queue (VTQ) supports all four architected AltiVec data stream operations
– Three-cycle GPR and AltiVec load latency (byte, half-word, word, vector) with one-cycle
throughput
– Four-cycle FPR load latency (single, double) with one-cycle throughput
– No additional delay for misaligned access within double-word boundary
– Dedicated adder calculates effective addresses (EAs)
– Supports store gathering
– Performs alignment, normalization, and precision conversion for floating-point data
– Executes cache control and TLB instructions
– Performs alignment, zero padding, and sign extension for integer data
– Supports hits under misses (multiple outstanding misses)
– Supports both big- and little-endian modes, including misaligned little-endian accesses
• Three issue queues FIQ, VIQ, and GIQ can accept as many as one, two, and three instructions, respectively,
in a cycle. Instruction dispatch requires the following:
— Instructions can be dispatched only from the three lowest IQ entries—IQ0, IQ1, and IQ2
— A maximum of three instructions can be dispatched to the issue queues per clock cycle
— Space must be available in the CQ for an instruction to dispatch (this includes instructions that are
assigned a space in the CQ but not in an issue queue)
• Rename buffers
— 16 GPR rename buffers
— 16 FPR rename buffers
— 16 VR rename buffers
• Dispatch unit
— Decode/dispatch stage fully decodes each instruction
• Completion unit
— The completion unit retires an instruction from the 16-entry completion queue (CQ) when all
instructions ahead of it have been completed, the instruction has finished execution, and no exceptions
are pending.
— Guarantees sequential programming model (precise exception model)
— Monitors all dispatched instructions and retires them in order
— Tracks unresolved branches and flushes instructions after a mispredicted branch
MPC7455 RISC Microprocessor Hardware Specifications, Rev. 4.1
4 Freescale Semiconductor
4페이지 Comparison with the MPC7400, MPC7410, MPC7450, MPC7451, and MPC7441
• Performance monitor can be used to help debug system designs and improve software efficiency
• In-system testability and debugging features through JTAG boundary-scan capability
• Testability
— LSSD scan design
— IEEE 1149.1 JTAG interface
— Array built-in self test (ABIST)—factory test only
• Reliability and serviceability
— Parity checking on system bus and L3 cache bus
— Parity checking on the L2 and L3 cache tag arrays
3 Comparison with the MPC7400, MPC7410, MPC7450,
MPC7451, and MPC7441
Table 1 compares the key features of the MPC7455 with the key features of the earlier MPC7400, MPC7410,
MPC7450, MPC7451, and MPC7441. To achieve a higher frequency, the number of logic levels per cycle is
reduced. Also, to achieve this higher frequency, the pipeline of the MPC7455 is extended (compared to the
MPC7400), while maintaining the same level of performance as measured by the number of instructions executed
per cycle (IPC).
Table 1. Microarchitecture Comparison
Microarchitectural Specs
MPC7455/MPC7445
MPC7450/MPC7451/
MPC7441
MPC7400/MPC7410
Basic Pipeline Functions
Logic inversions per cycle
18 18
Pipeline stages up to execute
Total pipeline stages (minimum)
Pipeline maximum instruction
throughput
5
7
3 + Branch
5
7
3 + Branch
Pipeline Resources
Instruction buffer size
Completion buffer size
Renames (integer, float, vector)
12
16
16, 16, 16
12
16
16, 16, 16
Maximum Execution Throughput
SFX
Vector
Scalar floating-point
3
2 (Any 2 of 4 Units)
1
3
2 (Any 2 of 4 Units)
1
Out-of-Order Window Size in Execution Queues
SFX integer units
Vector units
1 Entry × 3 Queues
In Order, 4 Queues
1 Entry × 3 Queues
In Order, 4 Queues
28
3
4
2 + Branch
6
8
6, 6, 6
2
2 (Permute/Fixed)
1
1 Entry × 2 Queues
In Order, 2 Queues
MPC7455 RISC Microprocessor Hardware Specifications, Rev. 4.1
Freescale Semiconductor
7
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