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UCN5822 데이터시트 PDF




Allegro에서 제조한 전자 부품 UCN5822은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 UCN5822 자료 제공

부품번호 UCN5822 기능
기능 (UCN5821) BiMOS II 8-BIT SERIAL-INPUT / LATCHED DRIVERS
제조업체 Allegro
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UCN5822 데이터시트, 핀배열, 회로
5821 AND
5822
CLOCK 1 CLK
SERIAL
DATA IN
2
LOGIC 3
GROUND
LOGIC
SUPPLY
4
VDD
SERIAL
DATA OUT
5
STROBE 6 ST
OUTPUT
ENABLE
7
OE
POWER 8
GROUND
SUB
16 OUT 1
15 OUT2
14 OUT 3
13 OUT4
12 OUT5
11 OUT6
10 OUT7
9 OUT8
Dwg. PP-026A
Note the DIP package and the SOIC package are
electrically identical and share common terminal
number assignments.
ABSOLUTE MAXIMUM RATINGS
at 25°C Free-Air Temperature
Output Voltage, VOUT
UCN5821A & UCN5821LW..... 50 V
UCN5822A & UCN5822LW..... 80 V
Logic Supply Voltage, VDD ............. 15 V
Input Voltage Range,
VIN .................. -0.3 V to VDD + 0.3 V
Continuous Output Current,
IOUT ..................................... 500 mA
Package Power Dissipation, PD
Package Code ‘A’ .................. 2.1 W
Package Code ‘LW’ ............... 1.5 W
Operating Temperature Range,
TA ............................ -20°C to +85°C
Storage Temperature Range,
TS .......................... -55°C to +150°C
Caution: CMOS devices have input static protection
but are susceptible to damage when exposed to
extremely high static electrical charges.
BiMOS II 8-BIT SERIAL-INPUT,
LATCHED DRIVERS
A merged combination of bipolar and MOS technology gives
these devices an interface flexibility beyond the reach of standard
logic buffers and power driver arrays. The UCN5821A,
UCN5821LW, UCN5822A, and UCN5822LW each have an
eight-bit CMOS shift register and CMOS control circuitry, eight
CMOS data latches, and eight bipolar current-sinking Darlington
output drivers. The UCN5821A/LW and UCN5822A/LW are
identical except for rated output voltage.
BiMOS II devices have much higher data-input rates than the
original BiMOS circuits. With a 5 V logic supply, they will
typically operate at better than 5 MHz. With a 12 V supply,
significantly higher speeds are obtained. The CMOS inputs are
compatible with standard CMOS and NMOS logic levels. TTL
circuits may require the use of appropriate pull-up resistors. By
using the serial data output, the drivers can be cascaded for
interface applications requiring additional drive lines.
The UCN5821/22A are furnished in a standard 16-pin plastic
DIP; the UCN5821/22LW are in a 16-lead wide-body SOIC for
surface-mount applications. The UCN5821A is also available for
operation from -40°C to +85°C. To order, change the prefix from
‘UCN’ to ‘UCQ’.
FEATURES
I To 3.3 MHz Data Input Rate
I CMOS, NMOS, TTL Compatible
I Internal Pull-Down Resistors
I Low-Power CMOS Logic & Latches
I High-Voltage Current-Sink Outputs
I Automotive Capable
Always order by complete part number, e.g., UCN5821A .
www.allegromicro.com




UCN5822 pdf, 반도체, 판매, 대치품
5821 AND 5822
8-BIT SERIAL-INPUT,
LATCHED DRIVERS
CLOCK
DATA IN
STROBE
AD
B
E
C
F
OUTPUT
ENABLE
OUTN
G
Dwg. No. A-12,627
TIMING CONDITIONS
(VDD = 5.0 V, TA = +25°C, Logic Levels are VDD and Ground)
A. Minimum Data Active Time Before Clock Pulse
(Data Set-Up Time) ....................................................................... 75 ns
B. Minimum Data Active Time After Clock Pulse
(Data Hold Time) ........................................................................... 75 ns
C. Minimum Data Pulse Width .............................................................. 150 ns
D. Minimum Clock Pulse Width ............................................................ 150 ns
E. Minimum Time Between Clock Activation and Strobe ....................... 30 ns
F. Minimum Strobe Pulse Width ........................................................... 100 ns
G. Typical Time Between Strobe Activation and
Output Transition .......................................................................... 1.0 µs
Serial Data present at the input is
transferred to the shift register on the
logic “0” to logic “1” transition of the
CLOCK input pulse. On succeeding
CLOCK pulses, the registers shift data
information towards the SERIAL DATA
OUTPUT. The SERIAL DATA must
appear at the input prior to the rising edge
of the CLOCK input waveform.
Information present at any register is
transferred to its respective latch when the
STROBE is high (serial-to-parallel con-
version). The latches will continue to
accept new data as long as the STROBE
is held high. Applications where the
latches are bypassed (STROBE tied high)
will require that the ENABLE input be
high during serial data entry.
When the ENABLE input is high, all
of the output buffers are disabled (OFF)
without affecting the information stored
in the latches or shift register. With the
ENABLE input low, the outputs are
controlled by the state of the latches.
Serial
Shift Register Contents
Data Clock
Input Input I1 I2 I3 .............. I8
TRUTH TABLE
Serial
Latch Contents
Data Strobe
Output Input I1 I2 I3 .............. I8
Output
Enable
Output Contents
I1 I2 I3 .............. I8
H
H R1 R2 .............. R7
R7
L
L R1 R2 .............. R7
R7
X
R1 R2 R3 .............. R8
R8
X X X .............. X
X
L R1 R2 R3 .............. R8
P1 P2 P3 .............. P8
P8
H P1 P2 P3 .............. P8
L
P1 P2 P3 .............. P8
X X X .............. X
H H H H .............. H
L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000

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UCN5822 전자부품, 판매, 대치품
5821 AND 5822
8-BIT SERIAL-INPUT,
LATCHED DRIVERS
www.allegromicro.com
The products described here are manufactured under one or more
U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to
time, such departures from the detail specifications as may be
required to permit improvements in the performance, reliability, or
manufacturability of its products. Before placing an order, the user is
cautioned to verify that the information being relied upon is current.
Allegro products are not authorized for use as critical components
in life-support devices or systems without express written approval.
The information included herein is believed to be accurate and
reliable. However, Allegro MicroSystems, Inc. assumes no responsi-
bility for its use; nor for any infringement of patents or other rights of
third parties which may result from its use.

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