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PDF TXC04216 Data sheet ( Hoja de datos )
| Número de pieza | TXC04216 | |
| Descripción | E1Mx16 Device E1 Mapper 16-Channel | |
| Fabricantes | Transwitch | |
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E1Mx16 Device
E1 Mapper 16-Channel
TXC-04216
FEATURES
• Add/drop sixteen 2.048 Mbit/s signals from an
STM-1 VC-4/AU-3, STS-3, or an STS-1
• Independent add and drop bus timing modes
• Selectable HDB3 positive/negative rail or NRZ E1
interface. Performance counter provided for illegal
coding violations.
• Digital desynchronizers
• J2 16-byte ETSI trail trace comparison
• Drop buses are monitored for parity, loss of clock,
upstream AIS and H4 multiframe errors
• TU Tandem Connection ETSI message
processing and generation
• Performance counters are provided for TU/VT
pointer movements, BIP-2 errors and Far End
Block Errors (REIs)
• TU/VTs are monitored for Loss Of Pointer, New
Data Flags (NDFs), AIS, Remote Defect
Indication (RDI), and size errors (S-bits)
• V5 Byte Signal Label Mismatch and Unequipped
detection
• E1 facility and line loopbacks, generation of BIP-2
and REI errors, and send RDI capability
• Intel / Motorola compatible microprocessor bus
interface with interrupt capability
• Programmable internal RISC processor
implements VT-POH and VT-alarm handling
• Boundary scan capability (IEEE 1149.1)
• Single +5V, ±5% power supply
• 388-lead plastic ball grid array
(35 x 35 mm) package
DATA SHEET
DESCRIPTION
The E1 Mapper 16-Channel device is designed for add/drop
multiplexer, terminal multiplexer, and dual and single unidi-
rectional ring applications. Four field-proven QE1M Quad E1
Mapper chips are interconnected in a single compact pack-
age to permit higher application board densities.
Sixteen E1 2.048 Mbit/s signals are mapped to and from
asynchronous Tributary Unit-12s (TU-12s) or Virtual Tribu-
tary 2s (VT2s). The E1Mx16 interfaces to a multiple-seg-
ment, byte-parallel SDH/SONET-formatted Telecom Bus at
the 19.44 Mbit/s byte rate for STM-1/STS-3 operation or at
the 6.48 Mbit/s byte rate for STS-1 operation. This Bus per-
mits the E1Mx16 to connect directly to other TranSwitch
devices in application designs. The E1 signals can be either
HDB3 positive/negative rail or NRZ format. The E1Mx16
provides performance counters, alarm detection, and the
ability to generate errors and Alarm Indication Signals (AIS).
E1 facility and line loopback capabilities are also provided.
APPLICATIONS
• STM-1/STS-3/STS-1 to 2.048 Mbit/s add/drop
mux/demux
• Unidirectional or bidirectional ring applications
• STM-1/STS-3/STS-1 termination terminal mode
multiplexer
• STM-1/STS-3/STS-1 test equipment
STM-1/STS-3/STS-1
External Clock
2.048 Mbit/s
TELECOM BUS SIDE
+5V
TRIBUTARY SIDE
7
A - side
13
• Channel 1
drop bus
A - side
add bus
B - side
mdrop bus
.coB - side
uadd bus
•
E1Mx16
•
•
14
E1 Mapper 16-Channel
•
•
•
•
P & N data
and clock for
receive and
transmit, plus
13
TXC-04216
•
•
•
receive data
14
•
•7
zero-output
• Channel 16 control
53
et4 Boundary Microprocessor
e Scan
interface
U.S. Patents No. 4,967,405; 5,033,064;
h5,040,170; 5,265,096; 5,289,507; 5,297,180; 5,528,598; 5,535,218
sU.S. and/or foreign patents issued or pending
taCopyright 2000 TranSwitch Corporation
E1Mx16 is a trademark of TranSwitch Corporation
aTranSwitch and TXC are registered trademarks of TranSwitch Corporation
Controls
Document Number:
PRELIMINARY TXC-04216-MB
Ed. 2, October 2000
.d TranSwitch Corporation • 3 Enterprise Drive • Shelton, Connecticut 06484 • USA
www Tel: 203-929-8810 • Fax: 203-926-9453 • www.transwitch.com
1 page  
DATA SHEET
E1Mx16
TXC-04216
FEATURES
The following features are supported by the E1Mx16:
SDH/SONET FORMATS:
• STM-1 AU-4 VC-4 TUG-3 TUG-2 format
• STM-1 AU-3 TUG-2
• STS-3
• STS-1
OPERATING MODES:
The E1Mx16 supports the following modes of operation which are programmable by the microprocessor.
• Drop mode only (Add bus tristated)
- Drop from A or B
• Add mode only
- Add to A or B
• Single unidirectional ring
- Drop from A, Add to A
- Drop from B, Add to B
• Multiplexer
- Drop from A, Add to B
- Drop from B, Add to A
• Dual protection ring
- Drop from A, Add to A and B
- Drop from B, Add to A and B
BUS TIMING:
The E1Mx16 provides the following bus timing modes by lead selection with software overwrite:
• Drop bus timing
- Add bus timing is derived from the same named Drop bus
• Add bus timing
- Add bus timing is independent of the Drop bus
SDH/SONET BUS INTERFACE:
• STM-1/STS-3
- 19.44 Mbyte/s parallel interface
• STS-1
- 6.48 Mbyte/s parallel interface
-5-
PRELIMINARY TXC-04216-MB
Ed. 2, October 2000
5 Page 
DATA SHEET
E1Mx16
TXC-04216
BLOCK DIAGRAM DESCRIPTION
The block diagram for the E1 Mapper 16-Channel device is shown in Figure 1. The E1Mx16 interfaces to four
buses, designated as A Drop, B Drop, A Add, and B Add. The four buses run at the STM-1/STS-3 rate of 19.44
Mbyte/s, or at the STS-1 rate of 6.48 Mbyte/s. For North American applications, the asynchronous E1 signals
are carried in floating Virtual Tributary 2 (VT2) format in a Synchronous Transport Signal - 1 (STS-1), or in an
STS-1 that is carried in a Synchronous Transport Signal - 3 (STS-3). For ITU-T applications, the E1 signals are
carried in floating mode Tributary Unit - 12 (TU-12) format in the STM-1 Virtual Container - 4 structure (VC-4)
using Tributary Unit Group - 3 (TUG-3), or in the STM-1 Virtual Container - 3 structure (VC-3) using Tributary
Unit Group - 2 (TUG-2) mapping schemes. Sixteen E1 signals can be dropped from one bus (A Drop or B
Drop), or from any combination of the two drop buses, to the E1 lines. Sixteen asynchronous E1 signals are
converted into TU-12 or VT2 format and are added to either one or both of the add buses, depending upon the
mode of operation. When the E1Mx16 is configured for drop bus timing, the add buses are, by definition, byte-
synchronous and multiframe-synchronous with their like-named drop buses, but are delayed by one byte time
because of internal processing. For example, if a byte in the STM-1 Virtual Container - 4 structure (VC-4) using
a Tributary Unit Group - 3 (TUG-3) TU-12/VT2 is to be added to the A Add bus, the time of its placement on the
bus is derived from the A Drop bus timing, and from software instructions specifying which TU/VT number is
being dropped/added. When the device is configured for add bus timing, the add bus, parity, and add indicator
signals are derived from the add clock, C1J1V1 and SPE signals.
The A Receive block is identical to the B Receive block. The TU/VT Terminate block is repeated 32 times, two
for each port (A and B sides). The Destuff, Desync, and HDB3 Coder blocks are repeated sixteen times, one
for each port. The interface between a drop bus and Receive block consists of 12 input leads, and an optional
output lead: a byte clock, byte-wide data, a C1J1 indicator which may be carrying a V1 indication making the
signal a C1J1V1 indicator, an SPE indicator, and an odd parity lead for the last-named ten leads. Parity is
selectable by control bits for even parity and for the data byte only. The output lead is an optional TU/VT select
indicator signal. The Drop C1J1V1 signal is used in conjunction with the Drop SPE signal to determine the
location of the various pulses. The C1 pulse identifies the location of the C1 byte when the SPE signal is low. A
single J1 pulse identifies the starting location of the J1 byte in the VC-4 format, when the SPE signal is high.
Three J1 pulses are provided for the STS-3 format, each identifying the starting location of the J1 byte in each
of the STS-1 signals.
The E1Mx16 can operate with a V1 pulse in the C1J1V1 signal, or it can use an internal H4 detector for deter-
mining the location of the V1 pulse. The V1 pulse location is used to determine the location of the pointer byte
V1. For STM-1 VC-4 operation, if the C1J1V1 signal is used, a single V1 pulse must occur during three drop
bus clock cycles every four frames following the J1 pulse when the SPE signal is high. For STS-3 operation,
three V1 pulses must be present every four frames. Each of the three V1 pulses must be present three clock
cycles after the corresponding J1 pulse, when the SPE signal is high. For example, in a VC-4 signal, the J1
pulse identifies the J1 byte location (defined as the starting location for the VC-4) in the POH bytes. In the next
column (first clock cycle) all the rows are assigned as fixed stuff. Similarly, in the next column (second clock
cycle) all the rows are assigned as fixed stuff. The next column (third clock cycle) defines the start of TUG-3 A.
This column is where the V1 pulse occurs every four frames. However, the actual V1 byte location is six clock
cycles after the V1 pulse.
For STS-1 operation, one V1 pulse must be present if the C1J1V1 signal is used. The V1 pulse must occur on
the next clock cycle after the J1 pulse, and when the SPE signal is high. The J1 pulse identifies the J1 byte
location (defined as the starting location for the STS-1) in the POH bytes. In the next column (first clock cycle)
the TUs start. Thus, the V1 pulse identifies the starting location of the first V1 byte in the signal. The rest of the
V1 bytes for the 21 TU-12/VT2s are also aligned with respect to the V1 pulse.
Each bus is monitored for parity errors, loss of clock, H4 multiframe alignment if selected, and an upstream
SDH/SONET AIS indication. The E1Mx16 can monitor either the TOH E1 bytes or the H1/H2 bytes for an AIS
indication. Which E1 byte and H1/H2 bytes are selected is a function of the TU/VT selected.
- 11 -
PRELIMINARY TXC-04216-MB
Ed. 2, October 2000
11 Page | ||
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| PDF Descargar | [ Datasheet TXC04216.PDF ] | |
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