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PDF TXC04251 Data sheet ( Hoja de datos )
| Número de pieza | TXC04251 | |
| Descripción | QT1M Device Quad T1 Mapper | |
| Fabricantes | Transwitch | |
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QT1M Device
Quad T1 Mapper
TXC-04251
DATA SHEET
FEATURES
• Add/drop four 1.544 Mbit/s signals from an
STS-1, an STS-3/AU-3, or an STM-1 VC-4
• Independent add and drop bus timing modes
• Selectable AMI or B8ZS positive/negative rail or
NRZ T1 interface. Performance counter provided
for coding violations
• Digital desynchronizer reduces systemic jitter in
the presence of multiple pointer movements. A
register is also provided to control the internal
FIFO leak rate
• Drop buses are monitored for parity, loss of clock,
upstream AIS and H4 multiframe errors
• Performance counters are provided for VT/TU
pointer movements, BIP-2 errors and Far End
Block Errors (FEBEs)
• VT/TUs are monitored for Loss Of Pointer, New
Data Flags (NDFs), AIS, Remote Defect
Indication (RDI), and size errors (S-bits)
• V5 Byte Signal Label Mismatch and Unequipped
detection
• T1 facility and line loopbacks, generation of BIP-2
and FEBE errors, and send RDI capability
• Multiplexed microprocessor bus interface with
interrupt capability
• IEEE 1149.1 standard boundary scan
• 160-pin plastic quad flat package
DESCRIPTION
The Quad T1 Mapper device is designed for add/drop
multiplexer, terminal multiplexer, and dual and single uni-
directional ring applications. Four T1 1.544 Mbit/s sig-
nals are mapped to and from asynchronous 1.5 Virtual
Tributaries (VT1.5s) or Tributary Unit-11s (TU-11s). The
QT1M interfaces to a multiple-segment, byte-parallel
SONET/SDH-formatted bus at the 19.44 Mbit/s byte rate
for STS-3/STM-1 operation or at the 6.48 Mbit/s byte
rate for STS-1 operation. The T1 1.544 Mbit/s signals
can be either AMI/B8ZS positive/negative rail- or NRZ-
formatted signals. The QT1M provides performance
counters, alarm detection, and the ability to generate
errors and Alarm Indication Signals (AIS). T1 facility and
line loopback capabilities are also provided.
The bus interface can connect to other TranSwitch
devices, such as the STM-1/STS-3/STS-3c Overhead
Terminator (SOT-3), TXC-03003B, to form an STS-
3/STM-1 add/drop or terminal system.
APPLICATIONS
• STS-1/STS-3/STM-1 to 1.544 Mbit/s add/drop
mux/demux
• Unidirectional or bidirectional ring applications
• STS-1/STS-3/STM-1 termination terminal mode
multiplexer
• STS-1/STS-3/STM-1 test equipment
STS-1/STS-3/STM - 1
SONET/SDH LINE SIDE +5V
External Clock
1.544 Mbit/s
TERMINAL SIDE
A - side
13
7
drop bus
A - side
14
QT1M
Port 1 P & N data
7 and clock for
add bus
mB - side
odrop bus
.cB - side
heet4uadd bus
Quad T1 Mapper
13
TXC-04251
14
5
Boundary
Scan
4
Microprocessor Controls
interface
Port 2 receive and
7
Port 3
transmit, plus
receive data
zero-output
7 Port 4 control
sU.S. Patents No.: 4,967,405; 5,033,064; 5,040,170; 5,265,096; 5,289,057
taU.S. and/or foreign patents issued or pending
aCopyright 2000 TranSwitch Corporation
.dTranSwitch and TXC are registered trademarks of TranSwitch Corporation
Document Number:
TXC-04251-MB
Ed. 4, March 2000
TranSwitch Corporation • 3 Enterprise Drive • Shelton, Connecticut 06484 • USA
www Tel: 203-929-8810 • Fax: 203-926-9453 • www.transwitch.com
1 page  
DATA SHEET
QT1M
TXC-04251
BLOCK DIAGRAM
A Receive
(A Drop)
B Receive
(B Drop)
VT/TU
Terminate
A Side
VT/TU
Terminate
B Side
Repeated for Port n s 1, 2, 3 and 4
Destuff
Desync
AMI/B8ZS
Coder
EXTCK
QUIETn
RPOn
RNOn
RCOn
13 14 13 14
Alarms
Controls,
& Timing
A Transmit
(A Add)
VT/TU Build
A Side
B Transmit
(B Add)
IEEE 1149.1
Boundary
Scan I/O
TCK
TMS
TDI
TDO
TRS
VT/TU Build
B Side
Alarms & Controls
UPAD(7-0)
SEL
µP RD
WR
I/O ALE
INT/INT
INTSH
Test
Access
Port
Stuff/Sync
A Side
AMI/B8ZS
Decoder
Stuff/Sync
B Side
Repeated for Port n = 1, 2, 3 and 4
TPIn
TNIn/TLOSn
TCIn
TEST
ABUST
HIGHZ
RESET
Figure 1. QT1M TXC-04251 Block Diagram
BLOCK DIAGRAM DESCRIPTION
The block diagram for the Quad T1 Mapper is shown in Figure 1. The Quad T1 Mapper interfaces to four buses,
designated as A Drop, B Drop, A Add, and B Add. The four buses run at the STS-3/STM-1 rate of 19.44
Mbyte/s, or at the STS-1 rate of 6.48 Mbyte/s. For North American applications, the asynchronous T1 signals
are carried in floating Virtual Tributary 1.5s (VT1.5s) in a Synchronous Transport Signal -1 (STS-1), or in
STS-1s that are carried in a Synchronous Transport Signal - 3 (STS-3). For ITU applications, the T1 signals are
carried in floating mode Tributary Unit -11s (TU-11s) in the STM-1 Virtual Container -4 structure (VC-4) using
Tributary Unit Group -3 (TUG-3), or in the STM-1 Virtual Container -3 structure (VC-3) using Tributary Unit
Group -2 (TUG-2) mapping schemes. Four T1 signals can be dropped from one bus (A Drop or B Drop), or
from both of the drop buses, to the T1 lines. Four asynchronous T1 signals are formatted into VT1.5s or TUs
and are added to either of the add buses, or both, depending upon the mode of operation. When the Quad T1
Mapper is configured for drop bus timing, the add buses are, by definition, byte- and multiframe-synchronous
with their like-named drop buses, but are delayed by one byte time because of internal processing. For exam-
ple, if a byte in the STM-1 Virtual Container -4 structure (VC-4) using Tributary Unit Group -3 (TUG-3),
VT1.5/TU-11 is to be added to the A Add bus, the time of its placement on the bus is derived from the A Drop
-5-
TXC-04251-MB
Ed. 4, March 2000
5 Page 
DATA SHEET
QT1M
TXC-04251
Symbol
AD(7-0)
ADSPE
Pin No.
43, 44, 46,
47, 48, 50,
51, 52
33
I/O/P
I
I
ADC1J1V1
32
I
ADIND
24
AACLK
28
O
I
AAPAR
55
O(T)
AA(7-0)
AASPE
56, 58,
59, 60,
62, 63,
64, 65
31
O(T)
I
Type *
TTL
TTL
TTL
CMOS
4mA
TTLs
CMOS
4mA
CMOS
4mA
Name/Function
A Drop Bus Data Byte: Byte-wide data that corresponds
to the STS-3/STM-1/STS-1 signal from the drop bus. The
first bit received (dropped) corresponds to bit 7.
A Drop Bus SPE Indicator: A signal that is active high
during each byte of the STS-3/STM-1/STS-1 payload,
and low during Transport Overhead times.
A Drop Bus C1J1V1 Indications: An active high timing
signal that carries STS-3/STM-1/STS-1 starting frame
and SPE information. This signal works in conjunction
with the ADSPE signal. The C1 pulse identifies the
location of the first C1 byte in the STS-3/STM-1 signal,
and the C1 byte in the STS-1 signal, when ADSPE is low.
The J1 signal identifies the starting location of the J1
signal when ADSPE is high. One or more V1 pulses may
be present depending upon the format. The V1 pulses
may be used in place of the H4 byte as the multiframe
indication.
A Drop Bus VT/TU Selection Indication: Enabled when
control bit ADnEN is written with a 1. An active low signal
that is clocked out for the time slots determined by VT/TU
selection (VTNn register) for each port.
A Add Bus Clock: When the add bus timing mode is
selected, this input must be provided for add bus timing.
This clock operates at 19.44 MHz for STS-3/STM-1
operation, and at 6.48 MHz for STS-1 operation. The add
bus SPE indication (AASPE), and the C1J1V1 indication
(AAC1J1V1) are clocked in on falling edges of this clock.
Add bus byte-wide data (AA7-AA0), add indicator
(AADD), and parity bit (AAPAR) are clocked out on rising
edges of the clock during the time slots that correspond to
the selected VT/TU. When drop bus timing is selected,
this input is disabled.
A Add Bus Parity Bit: An odd parity output signal that is
calculated over the byte-wide add data. This tristate pin is
only active when there is data being added to the add bus.
When control bit APE is 1 even parity is calculated.
A Add Bus Data Byte: Byte-wide data that corresponds
to the selected VT/TU.
TTL A Add Bus SPE Indicator: When the add bus timing
mode is selected, this signal must be provided for add bus
timing. This signal must be high during each byte of the
STS-3/STM-1/STS-1 payload, and low during Transport
Overhead byte times.
- 11 -
TXC-04251-MB
Ed. 4, March 2000
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet TXC04251.PDF ] | |
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