TE28F320B3xxx Datasheet PDF - Intel
| Part Number | TE28F320B3xxx | |
| Description | (TE28F Series) SMART 3 ADVANCED BOOT BLOCK 4-8-16-32-MBIT FLASH MEMORY FAMILY | |
| Manufacturers | Intel | |
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E
PRELIMINARY
SMART 3 ADVANCED BOOT BLOCK
4-, 8-, 16-, 32-MBIT
FLASH MEMORY FAMILY
28F400B3, 28F800B3, 28F160B3, 28F320B3
28F008B3, 28F016B3, 28F032B3
n Flexible SmartVoltage Technology
2.7 V–3.6 V Read/Program/Erase
12 V VPP Fast Production
Programming
n 2.7 V or 1.65 V I/O Option
Reduces Overall System Power
n High Performance
2.7 V–3.6 V: 90 ns Max Access Time
3.0 V–3.6 V: 80 ns Max Access Time
n Optimized Block Sizes
Eight 8-KB Blocks for Data,
Top or Bottom Locations
Up to Sixty-Three 64-KB Blocks for
Code
n Block Locking
VCC-Level Control through WP#
n Low Power Consumption
10 mA Typical Read Current
n Absolute Hardware-Protection
VPP = GND Option
VCC Lockout Voltage
n Extended Temperature Operation
–40 °C to +85 °C
n Flash Data Integrator Software
Flash Memory Manager
System Interrupt Manager
Supports Parameter Storage,
Streaming Data (e.g., Voice)
n Automated Program and Block Erase
Status Registers
n Extended Cycling Capability
Minimum 100,000 Block Erase
Cycles Guaranteed
n Automatic Power Savings Feature
Typical ICCS after Bus Inactivity
n Standard Surface Mount Packaging
48-Ball µBGA* Package
48-Lead TSOP Package
40-Lead TSOP Package
n Footprint Upgradeable
Upgrade Path for 4-, 8-, 16-, and 32-
Mbit Densities
n ETOX™ VI (0.25 µ) Flash Technology
The Smart 3 Advanced Boot Block, manufactured on Intel’s latest 0.25 µ technology, represents a feature-
rich solution at overall lower system cost. Smart 3 flash memory devices incorporate low voltage capability
(2.7 V read, program and erase) with high-speed, low-power operation. Several new features have been
added, including the ability to drive the I/O at 1.65 V, which significantly reduces system active power and
interfaces to 1.65 V controllers. A new blocking scheme enables code and data storage within a single
device. Add to this the Intel-developed Flash Data Integrator (FDI) software, and you have a cost-effective,
monolithic code plus data storage solution. Smart 3 Advanced Boot Block products will be available in 40-
lead and 48-lead TSOP and 48-ball µBGA* packages. Additional information on this product family can be
obtained by accessing Intel’s WWW page: http://www.intel.com/design/flash.
July 1998
Order Number: 290580-005
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E
SMART 3 ADVANCED BOOT BLOCK
1.0 INTRODUCTION
This datasheet contains the specifications for the
Advanced Boot Block flash memory family, which is
optimized for low power, portable systems. This
family of products features 1.65 V–2.5 V or 2.7 V–
3.6 V I/Os and a low VCC/VPP operating range of
2.7 V–3.6 V for read, program, and erase
operations. In addition this family is capable of fast
programming at 12 V. Throughout this document,
the term “2.7 V” refers to the full voltage range
2.7 V–3.6 V (except where noted otherwise) and
“VPP = 12 V” refers to 12 V ±5%. Section 1.0 and
2.0 provide an overview of the flash memory family
including applications, pinouts and pin descriptions.
Section 3.0 describes the memory organization and
operation for these products. Sections 4.0 and 5.0
contain the operating specifications. Finally,
Sections 6.0 and 7.0 provide ordering and other
reference information.
1.1 Smart 3 Advanced Boot Block
Flash Memory Enhancements
The Smart 3 Advanced Boot Block flash memory
features
• Enhanced blocking for easy segmentation of
code and data or additional design flexibility
• Program Suspend to Read command
• VCCQ input of 1.65 V–2.5 V on all I/Os. See
Figures 1 through 4 for pinout diagrams and
VCCQ location
• Maximum program and erase time specification
for improved data storage.
Feature
Table 1. Smart 3 Advanced Boot Block Feature Summary
28F008B3, 28F016B3, 28F400B3(2), 28F800B3,
28F032B3(1)
28F160B3, 28F320B3
Reference
VCC Read Voltage
2.7 V– 3.6 V
Section 4.2, 4.4
VCCQ I/O Voltage
1.65 V–2.5 V or 2.7 V– 3.6 V
Section 4.2, 4.4
VPP Program/Erase Voltage
2.7 V– 3.6 V or 11.4 V– 12.6 V
Section 4.2, 4.4
Bus Width
8-bit
16 bit
Table 3
Speed
80 ns, 90 ns, 100 ns, 110 ns
Section 4.5
Memory Arrangement
1024 Kbit x 8 (8 Mbit),
2048 Kbit x 8 (16 Mbit),
4096 Kbit x 8 (32 Mbit)
256 Kbit x 16 (4 Mbit),
512 Kbit x 16 (8 Mbit),
1024 Kbit x 16 (16 Mbit)
2048 Kbit x 16 (32 Mbit)
Section 2.2
Blocking (top or bottom)
Eight 8-Kbyte parameter blocks and
Seven 64-Kbyte blocks (4-Mbit) or
Fifteen 64-Kbyte blocks (8-Mbit) or
Thirty-one 64-Kbyte main blocks (16-Mbit)
Sixty-three 64-Kbyte main blocks (32-Mbit)
Section 2.2
Appendix D
Locking
WP# locks/unlocks parameter blocks
All other blocks protected using VPP
Section 3.3
Table 8
Operating Temperature
Extended: –40 °C to +85 °C
Section 4.2, 4.4
Program/Erase Cycling
100,000 cycles
Section 4.2, 4.4
Packages
40-lead TSOP(1), 48-Ball 48-Lead TSOP, 48-Ball Figure 3, Figure 4
µBGA* CSP(2)
µBGA CSP(2)
NOTES:
1. 4-Mbit and 32-Mbit density not available in 40-lead TSOP.
2. 4-Mbit density not available in µBGA* CSP.
PRELIMINARY
5
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