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PDF MC54HC4050 Data sheet ( Hoja de datos )
| Número de pieza | MC54HC4050 | |
| Descripción | (MC54HC4049 / MC54HC4050) Hex Buffers/Logic-Level Down Converters | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MC54HC4050 (archivo pdf) en la parte inferior de esta página. Total 6 Páginas | ||
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Hex Buffers/Logic-Level
Down Converters
High–Performance Silicon–Gate CMOS
The MC54/74HC4049 consists of six inverting buffers, and the
MC54/74HC4050 consists of six noninverting buffers. They are identical in
pinout to the MC14049UB and MC14050B metal–gate CMOS buffers. The
device inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
The input protection circuitry on these devices has been modified by
eliminating the VCC diodes to allow the use of input voltages up to 15 volts.
Thus, the devices may be used as logic–level translators that convert from a
high voltage to a low voltage while operating at the low–voltage power
supply. They allow MC14000–series CMOS operating up to 15 volts to be
interfaced with High–Speed CMOS at 2 to 6 volts. The protection diodes to
GND are Zener diodes, which protect the inputs from both positive and
negative voltage transients.
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 5 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 36 FETs or 9 Equivalent Gates (4049)
24 FETs or 6 Equivalent Gates (4050)
LOGIC DIAGRAMS
HC4049
(INVERTING BUFFER)
HC4050
(NONINVERTING BUFFER)
2 32
A0 Y0 A0 Y0
4 54
A1 Y1 A1 Y1
7
A2
6
Y2
7
A2
6
Y2
9
A3
10
Y3
9
A3
10
Y3
11
A4
12
Y4
11
A4
12
Y4
14
A5
15
Y5
14
A5
PIN 1 = VCC
PIN 8 = GND
PINS 13, 16 = NO CONNECTION
15
Y5
MC54/74HC4049
MC54/74HC4050
16
1
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
16
1
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
16
1
D SUFFIX
SOIC PACKAGE
CASE 751B–05
ORDERING INFORMATION
MC54HCXXXXJ
MC74HCXXXXN
MC74HCXXXXD
Ceramic
Plastic
SOIC
PIN ASSIGNMENT
VCC 1
Y0 2
A0 3
Y1 4
A1 5
Y2 6
A2 7
GND 8
16 NC
15 Y5
14 A5
13 NC
12 Y4
11 A4
10 Y3
9 A3
NC = NO CONNECTION
FUNCTION TABLE
A Y Outputs
Input HC4049 HC4060
LH
HL
L
H
10/95
© Motorola, Inc. 1995
1 REV 6
1 page  
MC54/74HC4049 MC54/74HC4050
–A
–
16
1
OUTLINE DIMENSIONS
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
9 ISSUE V
–B
–
8
CL
–T
SEAT–ING
PLANE
F
NK
E
G
D 16 PL
0.25 (0.010) M T A S
M
J 16 PL
0.25 (0.010) M T B S
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIM F MAY NARROW TO 0.76 (0.030) WHERE
THE LEAD ENTERS THE CERAMIC BODY.
INCHES
MILLIMETERS
DIM MIN MAX MIN MAX
A 0.750 0.785 19.05 19.93
B 0.240 0.295 6.10 7.49
C — 0.200 — 5.08
D 0.015 0.020 0.39 0.50
E 0.050 BSC 1.27 BSC
F 0.055 0.065 1.40 1.65
G 0.100 BSC
2.54 BSC
J 0.008 0.015 0.21 0.38
K 0.125 0.170 3.18 4.31
L 0.300 BSC 7.62 BSC
M 0° 15° 0° 15°
N 0.020 0.040 0.51 1.01
–A
–
16
1
H
G
9
B
8
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
ISSUE R
FC
S
–T
–
SEATING
PLANE
K
J
D 16 PL
0.25 (0.010) M T A M
L
M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
INCHES
MILLIMETERS
DIM MIN MAX MIN MAX
A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
F 0.040 0.070 1.02 1.77
G
0.100 BSC
2.54 BSC
H
0.050 BSC
1.27 BSC
J 0.008 0.015 0.21 0.38
K 0.110 0.130 2.80 3.30
L 0.295 0.305 7.50 7.74
M
0° 10°
0° 10°
S 0.020 0.040 0.51 1.01
–A
–
16
1
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
9
–B
–
8
P 8 PL
0.25 (0.010) M
BM
–T
SEAT–ING
PLANE
G
K
C
D 16 PL
0.25 (0.010) M T B S A S
M
R X 45°
F
J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
MILLIMETERS
INCHES
DIM MIN MAX MIN MAX
A 9.80 10.00 0.386 0.393
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G
1.27 BSC
0.050 BSC
J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0° 7° 0° 7°
P 5.80 6.20 0.229 0.244
R 0.25 0.50 0.010 0.019
High–Speed CMOS Logic Data
DL129 — Rev 6
5
MOTOROLA
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| PDF Descargar | [ Datasheet MC54HC4050.PDF ] | |
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