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PDF MC54HC4040A Data sheet ( Hoja de datos )
| Número de pieza | MC54HC4040A | |
| Descripción | 12-Stage Binary Ripple Counter | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
12-Stage Binary Ripple
Counter
High–Performance Silicon–Gate CMOS
The MC54/74C4040A is identical in pinout to the standard CMOS
MC14040. The device inputs are compatible with standard CMOS out-
puts; with pullup resistors, they are compatible with LSTTL outputs.
This device consists of 12 master–slave flip–flops. The output of each
flip–flop feeds the next and the frequency at each output is half of that of
the preceding one. The state counter advances on the negative–going
edge of the Clock input. Reset is asynchronous and active–high.
State changes of the Q outputs do not occur simultaneously because of
internal ripple delays. Therefore, decoded output signals are subject to
decoding spikes and may have to be gated with the Clock of the
HC4040A for some designs.
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance With JEDEC Standard No. 7A Requirements
• Chip Complexity: 398 FETs or 99.5 Equivalent Gates
LOGIC DIAGRAM
Clock 10
Reset 11
9 Q1
7 Q2
6 Q3
5 Q4
3 Q5
2 Q6
4 Q7
13 Q8
12 Q9
14 Q10
15 Q11
1 Q12
Pin 16 = VCC
Pin 8 = GND
VCC Q11 Q10 Q8 Q9 Reset Clock Q1
16 15 14 13 12 11 10 9
Pinout: 16–Lead Plastic Package
(Top View)
12345678
Q12 Q6 Q5 Q7 Q4 Q3 Q2 GND
MC54/74HC4040A
16
1
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
16
1
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
16
1
D SUFFIX
SOIC PACKAGE
CASE 751B–05
16
1
DT SUFFIX
TSSOP PACKAGE
CASE 948F–01
ORDERING INFORMATION
MC54HCXXXXAJ
MC74HCXXXXAN
MC74HCXXXXAD
MC74HCXXXXADT
Ceramic
Plastic
SOIC
TSSOP
Clock
X
FUNCTION TABLE
Reset
L
L
H
Output State
No Charge
Advance to Next State
All Outputs Are Low
10/95
© Motorola, Inc. 1995
1 REV 1
1 page  
MC54/74HC4040A
Qn
Qn+1
50%
tPLH
50%
SWITCHING WAVEFORMS (continued)
VCC
GND
tPHL
DEVICE
UNDER
TEST
TEST
POINT
OUTPUT
CL*
Figure 3.
*Includes all probe and jig capacitance
Figure 4. Test Circuit
Q1 Q2 Q3 Q10 Q11 Q12
9 7 6 14 15 1
Clock 10
Reset 11
CQ
CQ
CQ
CQ
CQ
CQ
CQ
R
CQ
R
CQ
CQ
Q4 = Pin 5
Q5 = Pin 3
Q6 = Pin 2
Q7 = Pin 4
Q8 = Pin 13
Q9 = Pin 12
Figure 5. Expanded Logic Diagram
CQ
C
VCC = Pin 16
GND = Pin 8
High–Speed CMOS Logic Data
DL129 — Rev 6
5
MOTOROLA
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