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A42MX16 데이터시트 PDF




Actel Corporation에서 제조한 전자 부품 A42MX16은 전자 산업 및 응용 분야에서
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PDF 형식의 A42MX16 자료 제공

부품번호 A42MX16 기능
기능 40MX and 42MX FPGA Families
제조업체 Actel Corporation
로고 Actel Corporation 로고


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A42MX16 데이터시트, 핀배열, 회로
v5.0
40MX and 42MX FPGA Families
Features
High Capacity
• Single-Chip ASIC Alternative
• 3,000 to 54,000 System Gates
• Up to 2.5 kbits Configurable Dual-Port SRAM
• Fast Wide-Decode Circuitry
• Up to 202 User-Programmable I/O Pins
High Performance
• 5.6 ns Clock-to-Out
• 250 MHz Performance
• 5 ns Dual-Port SRAM Access
• 100 MHz FIFOs
• 7.5 ns 35-Bit Address Decode
HiRel Features
• Commercial, Industrial, and Military Temperature Plastic
Packages
Product Profile
Device
A40MX02
Capacity
System Gates
SRAM Bits
3,000
N/A
Logic Modules
Sequential
Combinatorial
Decode
Clock-to-Out
295
9.5 ns
SRAM Modules
(64x4 or 32x8)
N/A
Dedicated Flip-Flops
Maximum Flip-Flops
mClocks
oUser I/O (Maximum)
.cPCI
uBoundary Scan Test (BST)
t4Packages (by pin count)
ePLCC
ePQFP
hVQFP
sTQFP
taCQFP
PBGA
147
1
57
No
No
44, 68
100
80
w.daFebruary 2001
ww © 2001 Actel Corporation
A40MX04
6,000
N/A
547
9.5 ns
N/A
273
1
69
No
No
44, 68, 84
100
80
• Commercial, Military Temperature and MIL-STD-883
Ceramic Packages
• QML Certification
• Ceramic Devices Available to DSCC SMD
Ease of Integration
• Mixed Voltage Operation (5.0V or 3.3V I/O)
• Synthesis-Friendly Architecture to Support ASIC Design
Methodologies
• Up to 100% Resource Utilization and 100% Pin Fixing
• Deterministic, User-Controllable Timing
• Unique In-System Diagnostic and Verification Capability
with Silicon Explorer II
• Low Power Consumption
• IEEE Standard 1149.1 (JTAG) Boundary Scan Testing
• 5.0V and 3.3V Programmable PCI-Compliant I/O
A42MX09
14,000
N/A
348
336
N/A
5.6 ns
N/A
348
516
2
104
No
No
84
100, 160
100
176
A42MX16
24,000
N/A
624
608
N/A
6.1 ns
N/A
624
928
2
140
No
No
84
100, 160, 208
100
176
A42MX24
36,000
N/A
954
912
24
6.1 ns
N/A
954
1,410
2
176
Yes
Yes
84
160, 208
176
A42MX36
54,000
2,560
1,230
1,184
24
6.3 ns
10
1,230
1,822
6
202
Yes
Yes
208, 240
208, 256
272
1




A42MX16 pdf, 반도체, 판매, 대치품
40MX and 42MX FPGA Families
Development Tool Support
The MX devices are fully supported by Actels line of FPGA
development tools, including the Actel DeskTOP series and
Designer Series tools. The Actel DeskTOP series is an
integrated design environment for PCs that includes design
entry, simulation, synthesis, and place-and-route tools.
Designer Series, Actels suite of FPGA development point
tools for PCs and Workstations, includes the ACTgen Macro
Builder, timing-driven place-and-route and analysis tools,
and device programming software.
In addition, the MX devices contain ActionProbe circuitry
that provides built-in access to every node in a design,
enabling 100 percent real-time observation and analysis of a
device's internal logic nodes without design iteration. The
probe circuitry is accessed by Silicon Explorer II, an
easy-to-use integrated verification and logic analysis tool
that can sample data at 100 MHz (asynchronous) or 66 MHz
(synchronous). Silicon Explorer II attaches to a PCs
standard COM port, turning the PC into a fully functional
18-channel logic analyzer. Silicon Explorer II allows
designers to complete the design verification process at
their desks and reduces verification time from several hours
per cycle to only a few seconds.
Plastic Device Resources
User I/Os
Device
PLCC PLCC PLCC PQFP PQFP PQFP PQFP VQFP VQFP TQFP PBGA
44-Pin 68-Pin 84-Pin 100-Pin 160-Pin 208-Pin 240-Pin 80-Pin 100-Pin 176-Pin 272-Pin
A40MX02
34
57
57
57
A40MX04
34
57
69
69
69
A42MX09
72
83 101
83 104
A42MX16
72
83 125 140
83 140
A42MX24
72
125 176
150
A42MX36
176 202
202
Package Definitions (Contact your Actel sales representative for product availability.)
PLCC = Plastic Leaded Chip Carrier, PQFP = Plastic Quad Flat Pack, TQFP = Thin Quad Flat Pack, VQFP = Very Thin Quad Flat Pack,
PBGA = Plastic Ball Grid Array
Ceramic Device Resources
User I/Os
CQFP CQFP
Device 208-Pin 256-Pin
A42MX36 176 202
Package Definitions (Contact your Actel sales representative for product availability.)
CQFP = Ceramic Quad Flat Pack
4 v5.0

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A42MX16 전자부품, 판매, 대치품
40MX and 42MX FPGA Families
Some of the 42MX devices contain D-modules, which are
arranged around the periphery of the devices. D-modules
contain wide-decode circuitry, which provides a fast,
wide-input AND function similar to that found in
product-term architectures (Figure 4). The D-module
allows 42MX devices to perform wide-decode functions at
speeds comparable to CPLDs and PALs. The output of the
D-module has a programmable inverter for active HIGH or
LOW assertion. The D-module output is hard-wired to an
output pin, but it can also be fed back into the array to be
incorporated into other logic.
Dual-Port SRAM Modules
The A42MX36 device contains dual-port SRAM modules that
have been optimized for synchronous or asynchronous
applications. The SRAM modules are arranged in 256-bit
blocks that can be configured as 32x8 or 64x4. SRAM
modules can be cascaded together to form memory spaces
of user-definable width and depth. A block diagram of the
42MX dual-port SRAM block is shown in Figure 5.
The 42MX SRAM modules are true dual-port structures
containing independent read and write ports. Each SRAM
module contains six bits of read and write addressing
(RDAD[5:0] and WRAD[5:0], respectively) for 64x4-bit
blocks. When configured in byte mode, the highest order
address bits (RDAD5 and WRAD5) are not used. The read
and write ports of the SRAM block contain independent
clocks (RCLK and WCLK) with programmable polarities
offering active HIGH or LOW implementation. The SRAM
block contains eight data inputs (WD[7:0]), and eight
outputs (RD[7:0]) which are connected to segmented
vertical routing tracks.
The 42MX dual-port SRAM blocks provide an optimal
solution for high-speed buffered applications requiring fast
FIFO and LIFO queues. Actels ACTgen Macro Builder
provides the capability to quickly design memory functions,
such as FIFOs, LIFOs, and RAM arrays. In addition, unused
SRAM blocks can be used to implement registers for other
logic within the design.
7 Inputs
Programmable
Inverter
Hard-Wire to I/O
Feedback to Array
Figure 4 D-Module Implementation
WD[7:0]
Latches
[7:0]
WRAD[5:0]
[5:0]
Latches
Write
Port
Logic
SRAM Module
32 x 8 or 64 x 4
(256 Bits)
Read
Port
Logic
[5:0] RDAD[5:0]
Latches
Read
Logic
REN
MODE
BLKEN
WEN
WCLK
Write
Logic
RD[7:0]
Routing Tracks
RCLK
Figure 5 42MX Dual-Port SRAM Block
v5.0
7

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관련 데이터시트

부품번호상세설명 및 기능제조사
A42MX16

40MX and 42MX FPGA Families

Actel Corporation
Actel Corporation

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